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mb9a310a series 32 - b it arm ? cortex ? - m 3 fm 3 microcontroller cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134 - 1709 ? 408 - 943 - 2600 document number: 002 - 04674 rev. *c revised june 12, 2017 the mb9a310a series are a highly integrated 32 - bit microcontroller that target for high - performance and cost - sensitive embedded control applications. the mb9a310a series are based on the arm cortex - m3 processor and on - chip flash memory and sram, and peripheral functions, including motor control timers, adcs and communication interfaces (usb, uart, csio, i 2 c, lin). the products w hich are described in this data sheet are placed into type1 product categories in "fm3 family peripheral manual ". f eatures 32 - bit arm ? cortex ? - m3 core ? processor version: r2p1 ? up to 40 mhz frequency operation ? integrated nested vectored interrupt controller (nvic): 1 nmi (non - maskable interrupt) and 48 peripheral interrupts and 16 priority levels ? 24 - bit system timer (sys tick): system timer for os task management on - chip memories [flash memory] ? up to 512 kbyte ? read cycle: 0 wait - cycle ? security function for code protection [sram] this series contain a total of up to 32 kbyte on - chip sram. on - chip sr am is composed of two independent sram (sram0, sram1). sram0 is connected to i - code bus and d - code bus of cortex - m3 core. sram1 is connected to system bus. ? sram0: up to 16 kbytes ? sram1: up to 16 kbytes usb interface u sb interface is composed of device and host. pll for usb is built - in, usb clock can be generated by multiplication of main clock. [usb device ] ? usb2.0 full - speed supported ? max 6 endpoint supported ? endpoint 0 is control transfer ? endpoint 1,2 can be selected bulk - transfer, interrupt - transfe r or isochronous - transfer ? endpoint 3,4 and 5 can be selected bulk - transfer, interrupt - transfer ? endpoint1 - 5 is comprised double buffer ? endpoint 0, 2 to 5 : 64bytes ? endpoint 1: 256bytes [usb host] ? usb2.0 full/low speed supported ? bulk - transfer, interrupt - trans fer and isochronous - transfer support ? usb device connected/dis - connected automatic ally detect ? in/out token handshake packet automatically ? max 256 - byte packet - length supported ? wake - up function supported multi - function serial interface (max eight channels) ? 4 channels with 16 steps 9 bit fifo (ch.4 - ch.7 ), 4 channels without fifo (ch. 0 - ch.3 ) ? operation mode is selectable from the followings for each channel. ? uart ? csio ? lin ? i 2 c
document number: 002 - 04674 rev. *c page 2 of 116 mb9a310a series [uart] ? full duplex double buffer ? selection with or without parity supported ? built - in dedicated baud rate generator ? external clock available as a serial clock ? hardware flow control : automatically control the transmission by cts/rts (only ch.4) * ? various error detection functions available (parity errors, framing errors, and overrun errors) *: mb9af311l a , f312l a and f314l a do not support hardware flow control [csio] ? full - duplex double buffer ? built - in dedicated baud rate generator ? overrun error detection function available [lin] ? lin protocol rev.2.1 supported ? full - duplex double buffer ? maste r/slave mode supported ? lin break fi eld generation (can be changed 13 - 16bit length) ? lin break delimite r generation (can be changed 1 - 4bit length) ? various error detection functions available (parity errors, framing errors, and overrun errors) [i 2 c] standard - mode (max 100kbps) / fast - mode (max 400 kbps) supported external bus interface* ? supports sram, nor flash device ? up to 8 chip selects ? 8 - /16 - bit data width ? up to 25 - bit address bit ? maximum area size : up to 256 mbytes ? supports address/data multiplex ? supports external rdy function *: mb9af311l a , f312l a and f314l a do not support external bus interface dma controller ( 8 channels) the dma controller has an independent bus from the cpu, so cpu and dma controller can process simultaneously. ? 8 independently config ured and operated channels ? transfer can be started by software or request from the built - in peripherals ? transfer address area: 32 bit (4 gbytes) ? transfer mode: block transfer/burst transfer/demand transfer ? transfer data type: byte/half - word/word ? transfer block count: 1 to 16 ? number of transfers: 1 to 65536 a/d converter (max 16 channels) [12 - bit a/d converter] ? successive approximation type ? built - in 3 units * ? conversion time: 1.0 s @ 5 v ? priority conversion available (priority at 2levels) ? scanning con version mode ? built - in fifo for conversion data storage (for scan conversion: 16steps, for priority conversion: 4 steps) *: mb9af311l a , f312l a , f314l a built - in 2unit s base timer (max 8 channels) operation mode is selectable from the followings for each channel. ? 16 - bit pwm timer ? 16 - bit ppg timer ? 16 - /32 - bit reload timer ? 16 - /32 - bit pwc timer
document number: 002 - 04674 rev. *c page 3 of 116 mb9a310a series multi - function timer (max 2units) the multi - function timer is composed of the following blocks. ? 16 - bit free - run timer 3 ch/unit ? input capture 4 ch /unit ? output com pare 6 ch /unit ? a/d activation compare 3 ch/unit ? waveform generator 3 ch /unit ? 16 - bit ppg timer 3 ch /unit the following function can be used to achieve the motor control. ? pwm signal output function ? dc chopper waveform output function ? dead time function ? input capture function ? a/d converte r activate function ? dtif (motor emergency stop) interrupt function quadrature position/ revolution counter (qprc) (max 2units ) the quadrature position/revolution counter (qprc) is used to measure the position of the position encoder. moreov er, it is possible to use up/down counter. ? the detection edge of the three external event input pins ain, bin and zin is configurable. ? 16 - bit position counter ? 16 - bit revolution counter ? two 16 - bit compare registers dual timer (32 - /16 - bit down counter) the dual timer consists of two programmable 32 - /16 - bit down counters. operation mode is selectable from the followings for each timer channel. ? free - running ? periodic (=reload) ? one - shot watch counter the watch counter is used for wake up from low - power consumption mode. interval timer: up to 64 s (max) @ sub clock: 32.768 khz watch dog t imer (2channels) a watchdog timer can generate interrupts or a reset when a time - out value is reached. this series consists of two different watchdogs , a "hardware" watchdog and a, "software" watchdog. the "hardware" watchdog timer is clocked by the built - in low speed cr oscillator. therefore, the "hardware" watchdog is active in any low - power consumption modes except stop mode . external interrupt contr oller unit ? up to 16 external interrupt input pins. ? include one non - maskable interrupt (nmi) input pin. general - purpose i/o port this series can use its pins as general - purpose i/o ports when they are not used for external bus or peripherals. moreover, the port relocate function is built in. it can set which i/o port the peripheral function can be allocated to. ? capable of pull - up control per pin ? capable of reading pin level directly ? b uilt - in the port relocate function ? up to 83 fast general purpose i / o ports @ 100 pin package ? some ports are 5v tolerant i/o (mb9af315ma/na, mb9af316ma/na only) please see " pin description " to confirm the corresponding pins. crc (cyclic redundancy check) accelerator the crc accelerator calculates the crc which has a heavy software processing load, and achieves a reduction of the integrity check processing load for reception data and storage. ccitt crc16 and ieee - 802.3 crc32 are supported. ? ccitt crc16 generator polynomial: 0x1021 ? ieee - 802.3 crc32 generator polynomial: 0x04c11db7
document number: 002 - 04674 rev. *c page 4 of 116 mb9a310a series cl ock and reset [clocks] selectable from five clock sources (2 external oscillators, 2 built - in cr oscillators, and main pll). ? main clock: 4 mhz to 48 mhz ? sub clock: 32.768 khz ? built - in high - speed cr clock: 4 mhz ? built - in low - speed cr clock: 100 khz ? main pll clock [resets] ? reset requests from initx p ins ? power - on reset ? software reset ? watchdog timers reset ? low - voltage detector reset ? clock supervisor reset clock super visor (csv) clocks generated by built - in cr oscillators are used to supervise abnormality of the external clocks. ? external clock failure ( clock stop) is detected, reset is asserted. ? external frequency anomaly is detect ed, interrupt or reset is asserted. low - voltage detector (lvd) this series include 2 - stage monitoring of voltage on the vcc. wh en the voltage falls below the voltage that has been set, low - voltage detector generates an interrupt or reset. ? lvd1: error reporting via interrupt ? lvd2: auto - reset operation low - power consumption m ode three low - power consumption modes supported. ? sleep ? tim er ? stop debug ? serial wire jtag debug port (swj - dp) ? embedded trace macrocells (etm).* *: mb9af311l a /m a , f312l a /m a, f314l a /m a , f315m a and f316m a support only swj - dp. power supply ? two power supplies ? vcc = 2.7 v to 5.5 v: correspond to the wide range voltage. ? usbvcc = 3.0 v to 3.6 v: for usb i/o power supply , when usb is used. = 2.7 v to 5.5 v: when gpio is used.
document number: 002 - 04674 rev. *c page 5 of 116 mb9a310a series contents 1. product lineup ................................ ................................ ................................ ................................ ................................ .. 7 2. packages ................................ ................................ ................................ ................................ ................................ ........... 8 3. pin assignment ................................ ................................ ................................ ................................ ................................ . 9 4. list of p in functions ................................ ................................ ................................ ................................ ....................... 15 5. i/o circuit type ................................ ................................ ................................ ................................ ................................ 40 6. handling precautions ................................ ................................ ................................ ................................ ..................... 45 6.1 precautions for product design ................................ ................................ ................................ ................................ ... 45 6.2 precautions for package mounting ................................ ................................ ................................ .............................. 46 6.3 precautions for use environment ................................ ................................ ................................ ................................ 47 7. handling devices ................................ ................................ ................................ ................................ ............................ 48 8. block diagram ................................ ................................ ................................ ................................ ................................ . 50 9. memory size ................................ ................................ ................................ ................................ ................................ .... 51 10. memory map ................................ ................................ ................................ ................................ ................................ .... 51 11. pin status in each cpu state ................................ ................................ ................................ ................................ ........ 55 12. electrical characteristics ................................ ................................ ................................ ................................ ............... 59 12.1 absolute maximum ratings ................................ ................................ ................................ ................................ ......... 59 12.2 recommended operating conditions ................................ ................................ ................................ .......................... 61 12.3 dc characteristics ................................ ................................ ................................ ................................ ....................... 62 12.3.1 current rating ................................ ................................ ................................ ................................ ............................... 62 12.3.2 pin characteristics ................................ ................................ ................................ ................................ ....................... 64 12.4 ac characteristics ................................ ................................ ................................ ................................ ....................... 65 12.4.1 main clock input characteristics ................................ ................................ ................................ ................................ .. 65 12.4.2 sub clock input characteristics ................................ ................................ ................................ ................................ ... 66 12.4.3 built - in cr oscillation characteristics ................................ ................................ ................................ .......................... 66 12.4.4 operating conditions of main pll and usb pll (in the case of using main clock for input clock of pll) .................. 67 12.4.5 operating conditions of main pll (in the case of using the built - in high speed cr for the input clock of the main pll) ................................ ................................ ................................ ................................ ........................... 67 12.4.6 reset input characteristics ................................ ................................ ................................ ................................ .......... 68 12.4.7 power - on reset timing ................................ ................................ ................................ ................................ ................ 68 12.4.8 external bus timing ................................ ................................ ................................ ................................ ..................... 69 12.4.9 base timer input timing ................................ ................................ ................................ ................................ .............. 76 12.4.10 csio/uart timing ................................ ................................ ................................ ................................ .................. 77 12.4.11 external input timing ................................ ................................ ................................ ................................ ................ 85 12.4.12 quadrature position/revolution counter timing ................................ ................................ ................................ ........ 86 12.4.13 i 2 c timing ................................ ................................ ................................ ................................ ................................ . 88 12.4.14 etm timing ................................ ................................ ................................ ................................ ............................... 89 12.4.15 jtag timing ................................ ................................ ................................ ................................ ............................. 90 12.5 12 - bit a/d converter ................................ ................................ ................................ ................................ .................... 91 12.6 usb characteristics ................................ ................................ ................................ ................................ ..................... 94 12.7 low - voltage detection characteristics ................................ ................................ ................................ ........................ 98 12.8 flash memory write/erase charac teristics ................................ ................................ ................................ ................. 99 12.8.1 write / erase time ................................ ................................ ................................ ................................ ......................... 99 12.8.2 erase/write cycles and data hold time ................................ ................................ ................................ ......................... 99 12.9 return time from low - power consumption mode ................................ ................................ ................................ .... 100 12.9.1 return factor: interrupt ................................ ................................ ................................ ................................ .............. 100 12.9.2 return factor: reset ................................ ................................ ................................ ................................ .................. 102 13. ordering information ................................ ................................ ................................ ................................ .................... 104
document number: 002 - 04674 rev. *c page 6 of 116 mb9a310a series 14. package dimensions ................................ ................................ ................................ ................................ .................... 105 15. errata ................................ ................................ ................................ ................................ ................................ .............. 112 15.1 part numbers affected ................................ ................................ ................................ ................................ .............. 112 15.2 qualification status ................................ ................................ ................................ ................................ .................... 112 15.3 errata summary ................................ ................................ ................................ ................................ ........................ 112 16. major changes ................................ ................................ ................................ ................................ .............................. 113 document history ................................ ................................ ................................ ................................ ............................... 115 sales, solutions, and legal information ................................ ................................ ................................ ........................... 116
document number: 002 - 04674 rev. *c page 7 of 116 mb9a310a series 1. p roduct l ineup memory s ize product name mb9af311la/ma/na mb9af312la/ma/na mb9af314la/ma/na on - chip flash memory 64 kbytes 128 kbytes 256 kbytes on - chip sram 16 kbytes 16 kbytes 32 kbytes product name mb9af315ma/na mb9af316ma/na on - chip flash memory 384 kbytes 512 kbytes on - chip sram 32 kbytes 32 kbytes function product name mb9af311la mb9af312la mb9af314la mb9af311ma mb9af312ma mb9af314ma mb9af315ma mb9af316ma mb9af311na mb9af312na mb9af314na mb9af315na mb9af316na pin count 64 80 100 cpu cortex - m3 freq. 40 mhz power supply voltage range 2.7 v to 5.5 v usb2.0 interface ( device /host) 1 ch. dmac 8 ch. external bus interface - addr:21 - bit (max) data:8 - bit cs:4 (max) support: sram, nor flash addr:25 - bit (max) data:8 - /16 - bit cs:8 (max) support: sram, nor flash multi - function serial interface (uart/csio/lin/i 2 c) 8 ch. (max) ch.4 to ch.7: fifo (16 steps x 9 - bit) ch.0 to ch.3: no fifo base timer (pwc/reload timer/pwm/ppg) 8 ch. (max) mf - timer a/d activation compare 3 ch. 1 unit 2 units (max) input capture 4 ch. free - run timer 3 ch. output compare 6 ch. waveform generator 3 ch. ppg 3 ch. qprc 2 ch. (max) dual timer 1 unit watch counter 1 unit crc accelerator yes watchdog timer 1 ch. (sw) + 1 ch. (hw) external interrupts 8 pins (max) + nmi 1 11 pins (max) + nmi 1 16 pins (max) + nmi 1 i/o ports 51 pins (max) 66 pins (max) 83 pins (max) 12 - bit a/d converter 9 ch. (2 units) 12 ch. (3 units) 16 ch. (3 units) csv (clock super visor) yes lvd (low - voltage detector) 2 ch. built - in cr high - speed 4 mhz low - speed 100 khz debug function swj - dp swj - dp/etm note: ? all signals of the peripheral function in each product cannot be allocated by limiting the pins of package. it is necessary to use the port relocate function of the i/o port according to your function use. see 12 . electrical characteristics 12.4 . ac characteristics 12.4.3 . built - in cr oscillation characteristics for accuracy of built - in cr.
document number: 002 - 04674 rev. *c page 8 of 116 mb9a310a series 2. packages product name package mb9af311la mb9af312la mb9af314la mb9af311ma mb9af312ma mb9af314ma mb9af315ma mb9af316ma mb9af311na mb9af312na mb9af314na mb9af315na mb9af316na lqfp: lqd064 (0.5 mm pitch) ? - - lqfp: lqg064 (0.65 mm pitch) ? - - qfn : vnc064 (0.5 mm pitch) ? - - lqfp: lqh080 (0.5 mm pitch) - ? - lqfp: lqi100 (0.5 mm pitch) - - ? qfp : pqh100 (0.65 mm pitch) - - ? ? bga : lbc112 (0.8 mm pitch) - - ? * ? : supported *: mb9af315na, mb9af316na are planning note: ? refer to 14 . package dimensions for detailed information on each package.
document number: 002 - 04674 rev. *c page 9 of 116 mb9a310a series 3. pin assignment lqi10 0 (top view) note : ? the number after the underscore ("_") in pin names such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple pins that provide the same function for the same channel. use the extended port fun ction register (epfr) to select the pin. vss p81/udp0 p80/udm0 usbvcc p60/sin5_0/tioa2_2/int15_1/mrdy_1 p61/sot5_0/tiob2_2/uhconx p62/sck5_0/adtg_3/moex_1 p63/int03_0/mwex_1 p0f/nmix/crout_1 p0e/cts4_0/tiob3_2/ic13_0/mdqm1_1 p0d/rts4_0/tioa3_2/ic12_0/mdqm0_1 p0c/sck4_0/tioa6_1/ic11_0/male_1 p0b/sot4_0/tiob6_1/ic10_0/mcsx0_1 p0a/sin4_0/int00_2/frck1_0/mcsx1_1 p09/traceclk/tiob0_2/rts4_2/mcsx2_1 p08/traced3/tioa0_2/cts4_2/mcsx3_1 p07/traced2/adtg_0/sck4_2/mclkout_1 p06/traced1/tiob5_2/sot4_2/int01_1/mcsx4_1 p05/traced0/tioa5_2/sin4_2/int00_1/mcsx5_1 p04/tdo/swo p03/tms/swdio p02/tdi/mcsx6_1 p01/tck/swclk p00/trstx/mcsx7_1 vcc 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 vcc 1 75 vss p50/int00_0/ain0_2/sin3_1/rto10_0/madata00_1 2 74 p20/int05_0/crout_0/ain1_1/mad24_1 p51/int01_0/bin0_2/sot3_1/rto11_0/madata01_1 3 73 p21/sin0_0/int06_1/bin1_1 p52/int02_0/zin0_2/sck3_1/rto12_0/madata02_1 4 72 p22/sot0_0/tiob7_1/zin1_1 p53/sin6_0/tioa1_2/int07_2/rto13_0/madata03_1 5 71 p23/sck0_0/tioa7_1/rto00_1 p54/sot6_0/tiob1_2/rto14_0/madata04_1 6 70 p1f/an15/adtg_5/frck0_1/mad23_1 p55/sck6_0/adtg_1/rto15_0/madata05_1 7 69 p1e/an14/rts4_1/dtti0x_1/mad22_1 p56/int08_2/dtti1x_0/madata06_1 8 68 p1d/an13/cts4_1/ic03_1/mad21_1 p30/ain0_0/tiob0_1/int03_2/madata07_1 9 67 p1c/an12/sck4_1/ic02_1/mad20_1 p31/bin0_0/tiob1_1/sck6_1/int04_2/madata08_1 10 66 p1b/an11/sot4_1/ic01_1/mad19_1 p32/zin0_0/tiob2_1/sot6_1/int05_2/madata09_1 11 65 p1a/an10/sin4_1/int05_1/ic00_1/mad18_1 p33/int04_0/tiob3_1/sin6_1/adtg_6/madata10_1 12 64 p19/an09/sck2_2/mad17_1 p34/frck0_0/tiob4_1/madata11_1 13 63 p18/an08/sot2_2/mad16_1 p35/ic03_0/tiob5_1/int08_1/madata12_1 14 62 avss p36/ic02_0/sin5_2/int09_1/madata13_1 15 61 avrh p37/ic01_0/sot5_2/int10_1/madata14_1 16 60 avcc p38/ic00_0/sck5_2/int11_1/madata15_1 17 59 p17/an07/sin2_2/int04_1/mad15_1 p39/dtti0x_0/adtg_2 18 58 p16/an06/sck0_1/mad14_1 p3a/rto00_0/tioa0_1 19 57 p15/an05/sot0_1/ic03_2/mad13_1 p3b/rto01_0/tioa1_1 20 56 p14/an04/sin0_1/int03_1/ic02_2/mad12_1 p3c/rto02_0/tioa2_1 21 55 p13/an03/sck1_1/ic01_2/mad11_1 p3d/rto03_0/tioa3_1 22 54 p12/an02/sot1_1/ic00_2/mad10_1 p3e/rto04_0/tioa4_1 23 53 p11/an01/sin1_1/int02_1/frck0_2/mad09_1 p3f/rto05_0/tioa5_1 24 52 p10/an00 vss 25 51 vcc 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 vcc p40/tioa0_0/rto10_1/int12_1 p41/tioa1_0/rto11_1/int13_1 p42/tioa2_0/rto12_1 p43/tioa3_0/rto13_1/adtg_7 p44/tioa4_0/rto14_1/mad00_1 p45/tioa5_0/rto15_1/mad01_1 c vss vcc p46/x0a p47/x1a initx p48/dtti1x_1/int14_1/sin3_2/mad02_1 p49/tiob0_0/ic10_1/ain0_1/sot3_2/mad03_1 p4a/tiob1_0/ic11_1/bin0_1/sck3_2/mad04_1 p4b/tiob2_0/ic12_1/zin0_1/mad05_1 p4c/tiob3_0/ic13_1/sck7_1/ain1_2/mad06_1 p4d/tiob4_0/frck1_1/sot7_1/bin1_2/mad07_1 p4e/tiob5_0/int06_2/sin7_1/zin1_2/mad08_1 pe0/md1 md0 pe2/x0 pe3/x1 vss lqfp - 100
document number: 002 - 04674 rev. *c page 10 of 116 mb9a310a series pqh100 (top view) note : ? the number after the underscore ("_") in pin names such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple pins that provide the same function for the same channel. use the extended port function register (epfr) to select the pin. p50/int00_0/ain0_2/sin3_1/rto10_0/madata00_1 vcc vss p81/udp0 p80/udm0 usbvcc p60/sin5_0/tioa2_2/int15_1/mrdy_1 p61/sot5_0/tiob2_2/uhconx p62/sck5_0/adtg_3/moex_1 p63/int03_0/mwex_1 p0f/nmix/crout_1 p0e/cts4_0/tiob3_2/ic13_0/mdqm1_1 p0d/rts4_0/tioa3_2/ic12_0/mdqm0_1 p0c/sck4_0/tioa6_1/ic11_0/male_1 p0b/sot4_0/tiob6_1/ic10_0/mcsx0_1 p0a/sin4_0/int00_2/frck1_0/mcsx1_1 p09/traceclk/tiob0_2/rts4_2/mcsx2_1 p08/traced3/tioa0_2/cts4_2/mcsx3_1 p07/traced2/adtg_0/sck4_2/mclkout_1 p06/traced1/tiob5_2/sot4_2/int01_1/mcsx4_1 p05/traced0/tioa5_2/sin4_2/int00_1/mcsx5_1 p04/tdo/swo p03/tms/swdio p02/tdi/mcsx6_1 p01/tck/swclk p00/trstx/mcsx7_1 vcc vss p20/int05_0/crout_0/ain1_1/mad24_1 p21/sin0_0/int06_1/bin1_1 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 p51/int01_0/bin0_2/sot3_1/rto11_0/madata01_1 81 50 p22/sot0_0/tiob7_1/zin1_1 p52/int02_0/zin0_2/sck3_1/rto12_0/madata02_1 82 49 p23/sck0_0/tioa7_1/rto00_1 p53/sin6_0/tioa1_2/int07_2/rto13_0/madata03_1 83 48 p1f/an15/adtg_5/frck0_1/mad23_1 p54/sot6_0/tiob1_2/rto14_0/madata04_1 84 47 p1e/an14/rts4_1/dtti0x_1/mad22_1 p55/sck6_0/adtg_1/rto15_0/madata05_1 85 46 p1d/an13/cts4_1/ic03_1/mad21_1 p56/int08_2/dtti1x_0/madata06_1 86 45 p1c/an12/sck4_1/ic02_1/mad20_1 p30/ain0_0/tiob0_1/int03_2/madata07_1 87 44 p1b/an11/sot4_1/ic01_1/mad19_1 p31/bin0_0/tiob1_1/sck6_1/int04_2/madata08_1 88 43 p1a/an10/sin4_1/int05_1/ic00_1/mad18_1 p32/zin0_0/tiob2_1/sot6_1/int05_2/madata09_1 89 42 p19/an09/sck2_2/mad17_1 p33/int04_0/tiob3_1/sin6_1/adtg_6/madata10_1 90 41 p18/an08/sot2_2/mad16_1 p34/frck0_0/tiob4_1/madata11_1 91 40 avss p35/ic03_0/tiob5_1/int08_1/madata12_1 92 39 avrh p36/ic02_0/sin5_2/int09_1/madata13_1 93 38 avcc p37/ic01_0/sot5_2/int10_1/madata14_1 94 37 p17/an07/sin2_2/int04_1/mad15_1 p38/ic00_0/sck5_2/int11_1/madata15_1 95 36 p16/an06/sck0_1/mad14_1 p39/dtti0x_0/adtg_2 96 35 p15/an05/sot0_1/ic03_2/mad13_1 p3a/rto00_0/tioa0_1 97 34 p14/an04/sin0_1/int03_1/ic02_2/mad12_1 p3b/rto01_0/tioa1_1 98 33 p13/an03/sck1_1/ic01_2/mad11_1 p3c/rto02_0/tioa2_1 99 32 p12/an02/sot1_1/ic00_2/mad10_1 p3d/rto03_0/tioa3_1 100 31 p11/an01/sin1_1/int02_1/frck0_2/mad09_1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 p3e/rto04_0/tioa4_1 p3f/rto05_0/tioa5_1 vss vcc p40/tioa0_0/rto10_1/int12_1 p41/tioa1_0/rto11_1/int13_1 p42/tioa2_0/rto12_1 p43/tioa3_0/rto13_1/adtg_7 p44/tioa4_0/rto14_1/mad00_1 p45/tioa5_0/rto15_1/mad01_1 c vss vcc p46/x0a p47/x1a initx p48/dtti1x_1/int14_1/sin3_2/mad02_1 p49/tiob0_0/ic10_1/ain0_1/sot3_2/mad03_1 p4a/tiob1_0/ic11_1/bin0_1/sck3_2/mad04_1 p4b/tiob2_0/ic12_1/zin0_1/mad05_1 p4c/tiob3_0/ic13_1/sck7_1/ain1_2/mad06_1 p4d/tiob4_0/frck1_1/sot7_1/bin1_2/mad07_1 p4e/tiob5_0/int06_2/sin7_1/zin1_2/mad08_1 pe0/md1 md0 pe2/x0 pe3/x1 vss vcc p10/an00 qfp - 100
document number: 002 - 04674 rev. *c page 11 of 116 mb9a310a series lqh080 (top view) note : ? the number after the underscore ("_") in pin names such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple pins that provide the same function for the same channel. use the extended port function register (epfr) to select the pin. vss p81/udp0 p80/udm0 usbvcc p60/sin5_0/tioa2_2/int15_1/mrdy_1 p61/sot5_0/tiob2_2/uhconx p62/sck5_0/adtg_3/moex_1 p63/int03_0/mwex_1 p0f/nmix/crout_1 p0e/cts4_0/tiob3_2/ic13_0/mdqm1_1 p0d/rts4_0/tioa3_2/ic12_0/mdqm0_1 p0c/sck4_0/tioa6_1/ic11_0/male_1 p0b/sot4_0/tiob6_1/ic10_0/mcsx0_1 p0a/sin4_0/int00_2/frck1_0/mcsx1_1 p07/adtg_0/mclkout_1 p04/tdo/swo p03/tms/swdio p02/tdi/mcsx6_1 p01/tck/swclk p00/trstx/mcsx7_1 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 vcc 1 60 p20/int05_0/crout_0/ain1_1/mad24_1 p50/int00_0/ain0_2/sin3_1/rto10_0/madata00_1 2 59 p21/sin0_0/int06_1/bin1_1 p51/int01_0/bin0_2/sot3_1/rto11_0/madata01_1 3 58 p22/sot0_0/tiob7_1/zin1_1 p52/int02_0/zin0_2/sck3_1/rto12_0/madata02_1 4 57 p23/sck0_0/tioa7_1 p53/sin6_0/tioa1_2/int07_2/rto13_0/madata03_1 5 56 p1b/an11/sot4_1/ic01_1/mad19_1 p54/sot6_0/tiob1_2/rto14_0/madata04_1 6 55 p1a/an10/sin4_1/int05_1/ic00_1/mad18_1 p55/sck6_0/adtg_1/rto15_0/madata05_1 7 54 p19/an09/sck2_2/mad17_1 p56/int08_2/dtti1x_0/madata06_1 8 53 p18/an08/sot2_2/mad16_1 p30/ain0_0/tiob0_1/int03_2/madata07_1 9 52 avss p31/bin0_0/tiob1_1/sck6_1/int04_2/madata08_1 10 51 avrh p32/zin0_0/tiob2_1/sot6_1/int05_2/madata09_1 11 50 avcc p33/int04_0/tiob3_1/sin6_1/adtg_6/madata10_1 12 49 p17/an07/sin2_2/int04_1/mad15_1 p39/dtti0x_0/adtg_2 13 48 p16/an06/sck0_1/mad14_1 p3a/rto00_0/tioa0_1 14 47 p15/an05/sot0_1/ic03_2/mad13_1 p3b/rto01_0/tioa1_1 15 46 p14/an04/sin0_1/int03_1/ic02_2/mad12_1 p3c/rto02_0/tioa2_1 16 45 p13/an03/sck1_1/ic01_2/mad11_1 p3d/rto03_0/tioa3_1 17 44 p12/an02/sot1_1/ic00_2/mad10_1 p3e/rto04_0/tioa4_1 18 43 p11/an01/sin1_1/int02_1/frck0_2/mad09_1 p3f/rto05_0/tioa5_1 19 42 p10/an00 vss 20 41 vcc 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 p44/tioa4_0/mad00_1 p45/tioa5_0/mad01_1 c vss vcc p46/x0a p47/x1a initx p48/dtti1x_1/int14_1/sin3_2/mad02_1 p49/tiob0_0/ic10_1/ain0_1/sot3_2/mad03_1 p4a/tiob1_0/ic11_1/bin0_1/sck3_2/mad04_1 p4b/tiob2_0/ic12_1/zin0_1/mad05_1 p4c/tiob3_0/ic13_1/sck7_1/ain1_2/mad06_1 p4d/tiob4_0/frck1_1/sot7_1/bin1_2/mad07_1 p4e/tiob5_0/int06_2/sin7_1/zin1_2/mad08_1 pe0/md1 md0 pe2/x0 pe3/x1 vss lqfp - 80
document number: 002 - 04674 rev. *c page 12 of 116 mb9a310a series lqd064 / lqg064 (top view) note: ? the number after the underscore ("_") in pin names such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple pins that provide the same function for the same channel. use the extended port function register (epfr) to select the pin. vss p81/udp0 p80/udm0 usbvcc p60/sin5_0/tioa2_2/int15_1 p61/sot5_0/tiob2_2/uhconx p62/sck5_0/adtg_3 p0f/nmix/crout_1 p0c/sck4_0/tioa6_1 p0b/sot4_0/tiob6_1 p0a/sin4_0/int00_2 p04/tdo/swo p03/tms/swdio p02/tdi p01/tck/swclk p00/trstx 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 vcc 1 48 p21/sin0_0/int06_1 p50/int00_0/ain0_2/sin3_1 2 47 p22/sot0_0/tiob7_1 p51/int01_0/bin0_2/sot3_1 3 46 p23/sck0_0/tioa7_1 p52/int02_0/zin0_2/sck3_1 4 45 p19/an09/sck2_2 p30/ain0_0/tiob0_1/int03_2 5 44 p18/an08/sot2_2 p31/bin0_0/tiob1_1/sck6_1/int04_2 6 43 avss p32/zin0_0/tiob2_1/sot6_1/int05_2 7 42 avrh p33/int04_0/tiob3_1/sin6_1/adtg_6 8 41 avcc p39/dtti0x_0/adtg_2 9 40 p17/an07/sin2_2/int04_1 p3a/rto00_0/tioa0_1 10 39 p15/an05/ic03_2 p3b/rto01_0/tioa1_1 11 38 p14/an04/int03_1/ic02_2 p3c/rto02_0/tioa2_1 12 37 p13/an03/sck1_1/ic01_2 p3d/rto03_0/tioa3_1 13 36 p12/an02/sot1_1/ic00_2 p3e/rto04_0/tioa4_1 14 35 p11/an01/sin1_1/int02_1/frck0_2 p3f/rto05_0/tioa5_1 15 34 p10/an00 vss 16 33 vcc 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 c vcc p46/x0a p47/x1a initx p49/tiob0_0/ain0_1 p4a/tiob1_0/bin0_1 p4b/tiob2_0/zin0_1 p4c/tiob3_0/sck7_1/ain1_2 p4d/tiob4_0/sot7_1/bin1_2 p4e/tiob5_0/int06_2/sin7_1/zin1_2 pe0/md1 md0 pe2/x0 pe3/x1 vss lqfp - 64
document number: 002 - 04674 rev. *c page 13 of 116 mb9a310a series lbc112 note: ? the number after the underscore ("_") i n pin names such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple pins that provide the same function for the same channel. use the extended port function register (epfr) to select the pin. p4a md0 x0 x1 vss md1 vss vcc l vss c x0a vss p41 p45 j vcc p3f vss p40 an00 k vcc vss x1a initx p42 p48 p4b p4e p43 p49 p4d an02 vss an01 an07 an06 avss h p3b p3c p3e vss p44 p4c g p37 p38 p3a p3d an08 an05 vss an04 an03 avcc an11 f p34 p35 p36 p39 an13 an10 an09 avrh e p30 p31 p32 p33 index p22 an14 an12 vss p20 p21 d p53 p54 p55 vss an15 p56 p63 p0a vss p06 p23 c p50 p51 vss p60 p62 p0d p09 p05 b vcc vss p52 p61 p0f p0c p08 tdo/ swo p0b p07 tms/ swdio trstx vcc vss tck/ swclk vss tdi 9 10 11 a vss udp0 udm0 usbvcc p0e 1 2 3 4 5 6 7 8 pfbga - 112
document number: 002 - 04674 rev. *c page 14 of 116 mb9a310a series vnc064 (top view) note: ? the number after the underscore ( " _ " ) in pin names such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple pins that provide the same function for the same channel. use the extended port function register (e pfr) to select the pin. vss p81/udp0 p80/udm0 usbvcc p60/sin5_0/tioa2_2/int15_1 p61/sot5_0/tiob2_2/uhconx p62/sck5_0/adtg_3 p0f/nmix/crout_1 p0c/sck4_0/tioa6_1 p0b/sot4_0/tiob6_1 p0a/sin4_0/int00_2 p04/tdo/swo p03/tms/swdio p02/tdi p01/tck/swclk p00/trstx 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 vcc 1 48 p21/sin0_0/int06_1 p50/int00_0/ain0_2/sin3_1 2 47 p22/sot0_0/tiob7_1 p51/int01_0/bin0_2/sot3_1 3 46 p23/sck0_0/tioa7_1 p52/int02_0/zin0_2/sck3_1 4 45 p19/an09/sck2_2 p30/ain0_0/tiob0_1/int03_2 5 44 p18/an08/sot2_2 p31/bin0_0/tiob1_1/sck6_1/int04_2 6 43 avss p32/zin0_0/tiob2_1/sot6_1/int05_2 7 42 avrh p33/int04_0/tiob3_1/sin6_1/adtg_6 8 41 avcc p39/dtti0x_0/adtg_2 9 40 p17/an07/sin2_2/int04_1 p3a/rto00_0/tioa0_1 10 39 p15/an05/ic03_2 p3b/rto01_0/tioa1_1 11 38 p14/an04/int03_1/ic02_2 p3c/rto02_0/tioa2_1 12 37 p13/an03/sck1_1/ic01_2 p3d/rto03_0/tioa3_1 13 36 p12/an02/sot1_1/ic00_2 p3e/rto04_0/tioa4_1 14 35 p11/an01/sin1_1/int02_1/frck0_2 p3f/rto05_0/tioa5_1 15 34 p10/an00 vss 16 33 vcc 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 c vcc p46/x0a p47/x1a initx p49/tiob0_0/ain0_1 p4a/tiob1_0/bin0_1 p4b/tiob2_0/zin0_1 p4c/tiob3_0/sck7_1/ain1_2 p4d/tiob4_0/sot7_1/bin1_2 p4e/tiob5_0/int06_2/sin7_1/zin1_2 pe0/md1 md0 pe2/x0 pe3/x1 vss qfn - 64
document number: 002 - 04674 rev. *c page 15 of 116 mb9a310a series 4. list of pin functions list of pin numbers the number after the underscore ("_") in pin names such as xxx_1 and xxx_2 indicates the relocated port number. for these pin s, there are multiple pins that provide the same function for the same channel. use the extended port function register (epfr) to select the pin. pin no pin name i/o circuit type pin state type lqfp - 100 qfp - 100 bga - 112 lqfp - 80 l qfp - 64 qfn - 64 1 79 b1 1 1 vcc - 2 80 c1 2 2 p50 e h int00_0 ain0_2 sin3_1 - rto10_0 (ppg10_0) m a data 00_1 3 81 c2 3 3 p51 e h int01_0 bin0_2 sot3_1 (sda3_1) - rto11_0 (ppg10_0) m a data 0 1 _1 4 82 b3 4 4 p52 e h int02_0 zin0_2 sck3_1 (scl3_1) - rto12_0 (ppg12_0) m a data 0 2 _1 5 83 d1 5 - p53 e h sin6_0 tioa1_2 int07_2 rto13_0 (ppg12_0) m a data 0 3 _1 6 84 d2 6 - p54 e i sot6_0 (sda6_0) tiob1_2 rto14_0 (ppg14_0) m a data 0 4 _1
document number: 002 - 04674 rev. *c page 16 of 116 mb9a310a series pin no pin name i/o circuit type pin state type lqfp - 100 qfp - 100 bga - 112 lqfp - 80 l qfp - 64 qfn - 64 7 85 d3 7 - p55 e i sck6_0 (scl6_0) adtg _ 1 rto15_0 (ppg14_0) m a data 0 5 _1 8 86 d5 8 - p56 e h int08_2 dtti1x_0 madata06_1 9 87 e1 9 5 p30 e h ain0_0 tiob0_1 int03_2 - madata07_1 10 88 e2 10 6 p31 e h bin0_0 tiob1_1 sck6_1 (scl6_1) int04_2 - madata08_1 11 89 e3 11 7 p32 e h zin0_0 tiob2_1 sot6_1 (sda6_1) int05_2 - madata09_1 12 90 e4 12 8 p33 e h int04_0 tiob3_1 sin6_1 adtg_6 - madata10_1 13 91 f1 - - p34 e i frck0_0 tiob4_1 madata11_1
document number: 002 - 04674 rev. *c page 17 of 116 mb9a310a series pin no pin name i/o circuit type pin state type lqfp - 100 qfp - 100 bga - 112 lqfp - 80 l qfp - 64 qfn - 64 14 92 f2 - - p35 e h ic03_0 tiob5_1 int08_1 mad ata12_1 15 93 f3 - - p36 e h ic02_0 sin5_2 int09_1 madata13_1 16 94 g1 - - p37 e h ic01_0 sot5_2 (sda5_2) int10_1 m adata14_1 17 95 g2 - - p38 e h ic00_0 sck5_2 (scl5_2) int11_1 madata15_1 18 96 f4 13 9 p39 e i dtti0x_0 adtg_2 19 97 g3 14 10 p3a g i rto00_0 (ppg00_0) tioa0_1 20 98 h1 15 11 p3b g i rto01_0 (ppg00_0) tioa1_1 21 99 h2 16 12 p3c g i rto02_0 (ppg02_0) tioa2_1 22 100 g4 17 13 p3d g i rto03_0 (ppg02_0) tioa3_1 - - b2 - - vss -
document number: 002 - 04674 rev. *c page 18 of 116 mb9a310a series pin no pin name i/o circuit type pin state type lqfp - 100 qfp - 100 bga - 112 lqfp - 80 l qfp - 64 qfn - 64 23 1 h3 18 14 p3e g i rto04_0 (ppg04_0) tioa4_1 24 2 j2 19 15 p3f g i rto05_0 (ppg04_0) tioa5_1 25 3 l1 20 16 vss - 26 4 j1 - - vcc - 27 5 j4 - - p40 g h tioa0_0 rto10_1 (ppg10_1) int12_1 28 6 l5 - - p41 g h tioa1_0 rto11_1 (ppg10_1) int13_1 29 7 k5 - - p42 g i tioa2_0 rto12_1 (ppg12_1) 30 8 j5 - - p43 g i tioa3_0 rto13_1 (ppg12_1) adtg_7 31 9 h5 21 - p44 g i tioa4_0 mad00_1 - rto14_1 (ppg14_1) 32 10 l6 22 - p45 g i tioa5_0 mad01_1 - rto15_1 (ppg14_1) - - k2 - - vss - - - j3 - - vss - - - h4 - - vss -
document number: 002 - 04674 rev. *c page 19 of 116 mb9a310a series pin no pin name i/o circuit type pin state type lqfp - 100 qfp - 100 bga - 112 lqfp - 80 l qfp - 64 qfn - 64 33 11 l2 23 17 c - 34 12 l4 24 - vss - 35 13 k1 25 18 vcc - 36 14 l3 26 19 p46 d m x0a 37 15 k3 27 20 p47 d n x1a 38 16 k4 28 21 initx b c 39 17 k6 29 - p48 e h dtti1x_1 int14_1 sin3_2 mad02_1 40 18 j6 30 22 p49 e i tiob0_0 ain0_1 - ic10_1 sot3_2 (sda3_2) mad03_1 41 19 l7 31 23 p4a e i tiob1_0 bin0_1 - ic11_1 sck3_2 (scl3_2) mad04_1 42 20 k7 32 24 p4b e i tiob2_0 zin0_1 - ic12_1 mad05_1 43 21 h6 33 25 p4c e / i* i tiob3_0 sck7_1 (scl7_1) ain1_2 - ic13_1 mad06_1
document number: 002 - 04674 rev. *c page 20 of 116 mb9a310a series pin no pin name i/o circuit type pin state type lqfp - 100 qfp - 100 bga - 112 lqfp - 80 l qfp - 64 qfn - 64 44 22 j7 34 26 p4d e / i* i tiob4_0 sot7_1 (sda7_1) bin1_2 - frck1_1 mad07_1 45 23 k8 35 27 p4e e / i* i tiob5_0 int06_2 sin7_1 zin1_2 - mad08_1 46 24 k9 36 28 md1 c p pe0 47 25 l8 37 29 md0 j d 48 26 l9 38 30 x0 a a pe2 49 27 l10 39 31 x1 a b pe3 50 28 l11 40 32 vss - 51 29 k11 41 33 vcc - 52 30 j11 42 34 p10 f k an00 53 31 j10 43 35 p11 f l an01 sin1_1 int02_1 frck0_2 - mad09_1 54 32 j8 44 36 p12 f k an02 sot1_1 (sda1_1) ic00_2 - mad10_1 - - k10 - - vss - - - j9 - - vss -
document number: 002 - 04674 rev. *c page 21 of 116 mb9a310a series pin no pin name i/o circuit type pin state type lqfp - 100 qfp - 100 bga - 112 lqfp - 80 l qfp - 64 qfn - 64 55 33 h10 45 37 p13 f k an03 sck1_1 (scl1_1) ic01_2 - mad11_1 56 34 h9 46 38 p14 f l an04 int03_1 ic02_2 - sin0_1 mad12_1 57 35 h7 47 39 p15 f k an05 ic03_2 - sot0_1 (sda0_1) mad13_1 58 36 g10 48 - p16 f k an06 sck0_1 (scl0_1) mad14_1 59 37 g9 49 40 p17 f l an07 sin2_2 int04_1 - mad15_1 60 38 h11 50 41 avcc - 61 39 f11 51 42 avrh - 62 40 g11 52 43 avss - 63 41 g8 53 44 p18 f k an08 sot2_2 (sda2_2) - mad16_1 64 42 f10 54 45 p19 f k an09 sck2_2 (scl2_2) - mad17_1 - - h8 - - vss -
document number: 002 - 04674 rev. *c page 22 of 116 mb9a310a series pin no pin name i/o circuit type pin state type lqfp - 100 qfp - 100 bga - 112 lqfp - 80 l qfp - 64 qfn - 64 65 43 f9 55 - p1a f l an10 sin4_1 int05_1 ic00_1 mad18_1 66 44 e11 56 - p1b f k an11 sot4_1 (sda4_1) ic01_1 mad19_1 67 45 e10 - - p1c f k an12 sck4_1 (scl4_1) ic02_1 mad20_1 68 46 f8 - - p1d f k an13 cts4_1 ic03_1 mad21_1 69 47 e9 - - p1e f k an14 rts4_1 dtti0x_1 mad22_1 70 48 d11 - - p1f f k an15 adtg_5 frck0_1 mad23_1 - - b10 - - vss - - - c9 - - vss -
document number: 002 - 04674 rev. *c page 23 of 116 mb9a310a series pin no pin name i/o circuit type pin state type lqfp - 100 qfp - 100 bga - 112 lqfp - 80 l qfp - 64 qfn - 64 7 1 49 d10 57 46 p23 e i sck0_0 (scl0_0) tioa7_1 - - rto00_1 (ppg00_1) 7 2 50 e8 58 47 p22 e i sot0_0 (sda0_0) tiob7_1 - zin1_1 7 3 51 c11 59 48 p21 e h sin0_0 int06_1 - bin1_1 7 4 52 c10 60 - p20 e h int05_0 crout _0 ain1_1 mad24_1 75 53 a11 - - vss - 76 54 a10 - - vcc - 77 55 a9 61 49 p00 e e trstx - mcsx7_1 78 56 b9 62 50 p01 e e tck swclk 79 57 b11 63 51 p02 e e tdi - mcsx6_1 80 58 a8 64 52 p03 e e tms swdio 81 59 b8 65 53 p04 e e tdo swo 82 60 c8 - - p05 e f traced0 tioa5_2 sin4_2 int00_1 mcsx5_1 - - d8 - - vss -
document number: 002 - 04674 rev. *c page 24 of 116 mb9a310a series pin no pin name i/o circuit type pin state type lqfp - 100 qfp - 100 bga - 112 lqfp - 80 l qfp - 64 qfn - 64 83 61 d9 - - p06 e f traced1 tiob5_2 sot4_2 (sda4_2) int01_1 mcsx4_1 84 62 a7 66 - p07 e g adtg_0 mclkout_1 - traced2 sck4_2 (scl4_2) 85 63 b7 - - p08 e g traced3 tioa0_2 cts4_2 mcsx3_1 86 64 c7 - - p09 e g traceclk tiob0_2 rts4_2 mcsx2_1 87 65 d7 67 54 p0a e / i * h sin4_0 int00_2 - frck1_0 m csx1_1 88 66 a6 68 55 p0b e / i* i sot4_0 (sda4_0) tiob6_1 - ic10_0 m csx0_1 89 67 b6 69 56 p0c e / i* i sck4_0 (scl4_0) tioa6_1 - ic11_0 ma le_1 - - d4 - - vss - - - c3 - - vss -
document number: 002 - 04674 rev. *c page 25 of 116 mb9a310a series pin no pin name i/o circuit type pin state type lqfp - 100 qfp - 100 bga - 112 lqfp - 80 l qfp - 64 qfn - 64 90 68 c6 70 - p0d e i rts4_0 tioa3_2 ic12_0 mdqm0_1 91 69 a5 71 - p0e e i cts4_0 tiob3_2 ic13_0 mdqm1_1 92 70 b5 72 57 p0f e j nmix crout_1 93 71 d6 73 - p63 e h int03_0 mwex_1 94 72 c5 74 58 p62 e i sck5_0 (scl5_0) adtg_3 - moex_1 95 73 b4 75 59 p61 e i sot5_0 (sda5_0) tiob2_2 96 74 c4 76 60 p60 e / i* h sin5_0 tioa2_2 int15_1 - mrdy_1 97 75 a4 77 61 usb vcc - 98 76 a3 78 62 p80 h o udm0 99 77 a2 79 63 p81 h o udp0 100 78 a1 80 64 vss - *: 5 v tolerant i/o on mb9af315ma/na and mb9af3 16ma/na
document number: 002 - 04674 rev. *c page 26 of 116 mb9a310a series list of pin functions the number after the underscore ("_") in pin names such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple pins that provide the same function for the same channel. use the extended port function register (epfr) t o select the pin. module pin name functi on pin no lqfp - 100 qfp - 100 bga - 1 12 lqfp - 80 lq fp - 64 qfn - 64 adc adtg_0 a/d converter external trigger input pin 84 62 a7 66 - adtg_1 7 85 d3 7 - adtg_2 18 96 f4 13 9 adtg_3 94 72 c5 74 58 adtg_4 - - - - - adtg_5 70 48 d11 - - adtg_6 12 90 e4 12 8 adtg_7 30 8 j5 - - adtg_8 - - - - - an00 a/d converter analog input pin. anxx describes adc ch.xx. 52 30 j11 42 34 an01 53 31 j10 43 35 an02 54 32 j8 44 36 an03 55 33 h10 45 37 an04 56 34 h9 46 38 an05 57 35 h7 47 39 an06 58 36 g10 48 - an07 59 37 g9 49 40 an08 63 41 g8 53 44 an09 64 42 f10 54 45 an10 65 43 f9 55 - an11 66 44 e11 56 - an12 67 45 e10 - - an13 68 46 f8 - - an14 69 47 e9 - - an15 70 48 d11 - - base timer 0 tioa0_0 base timer ch.0 tioa pin 27 5 j4 - - tioa0_1 19 97 g3 14 10 tioa0_2 85 63 b7 - - tiob0_0 base timer ch.0 tiob pin 40 18 j6 30 22 tiob0_1 9 87 e1 9 5 tiob0_2 86 64 c7 - - base timer 1 tioa1_0 base timer ch.1 tioa pin 28 6 l5 - - tioa1_1 20 98 h1 15 11 tioa1_2 5 83 d1 5 - tiob1_0 base timer ch.1 tiob pin 41 19 l7 31 23 tiob1_1 10 88 e2 10 6 tiob1_2 6 84 d2 6 -
document number: 002 - 04674 rev. *c page 27 of 116 mb9a310a series module pin name function pin no lqfp - 100 qfp - 100 bga - 1 12 lqfp - 80 lq fp - 64 qfn - 64 base timer 2 tioa2_0 base timer ch.2 tioa pin 29 7 k5 - - tioa2_1 21 99 h2 16 12 tioa2_2 96 74 c4 76 60 tiob2_0 base timer ch.2 tiob pin 42 20 k7 32 24 tiob2_1 11 89 e3 11 7 tiob2_2 95 73 b4 75 59 base timer 3 tioa3_0 base timer ch.3 tioa pin 30 8 j5 - - tioa3_1 22 100 g4 17 13 tioa3_2 90 68 c6 70 - tiob3_0 base timer ch.3 tiob pin 43 21 h6 33 25 tiob3_1 12 90 e4 12 8 tiob3_2 91 69 a5 71 - base timer 4 tioa4_0 base timer ch.4 tioa pin 31 9 h5 21 - tioa4_1 23 1 h3 18 14 tioa4_2 - - - - - tiob4_0 base timer ch.4 tiob pin 44 22 j7 34 26 tiob4_1 13 91 f1 - - tiob4_2 - - - - - base timer 5 tioa5_0 base timer ch.5 tioa pin 32 10 l6 22 - tioa5_1 24 2 j2 19 15 tioa5_2 82 60 c8 - - tiob5_0 base timer ch.5 tiob pin 45 23 k8 35 27 tiob5_1 14 92 f2 - - tiob5_2 83 61 d9 - - base timer 6 tioa6_1 base timer ch.6 tioa pin 89 67 b6 69 56 tiob6_1 base timer ch.6 tiob pin 88 66 a6 68 55 base timer 7 tioa7_0 base timer ch.7 tioa pin - - - - - tioa7_1 71 49 d10 57 46 tioa7_2 - - - - - tiob7_0 base timer ch.7 tiob pin - - - - - tiob7_1 72 50 e8 58 47 tiob7_2 - - - - -
document number: 002 - 04674 rev. *c page 28 of 116 mb9a310a series module pin name function pin no lqfp - 100 qfp - 100 bga - 1 12 lqfp - 80 lq fp - 64 qfn - 64 debugger swclk serial wire debug interface clock input 78 56 b9 62 50 swdio serial wire debug interface data input / output 80 58 a8 64 52 swo serial wire viewer output 81 59 b8 65 53 tck jtag test clock input 78 56 b9 62 50 tdi jtag test data input 79 57 b11 63 51 tdo jtag debug data output 81 59 b8 65 53 tms jtag test mode state input/output 80 58 a8 64 52 traceclk trace clk output of etm 86 64 c7 - - traced0 trace data output of etm 82 60 c8 - - traced1 83 61 d9 - - traced2 84 62 a7 - - traced3 85 63 b7 - - trstx jtag test reset input 77 55 a9 61 49 external bus mad00_1 external bus interface address bus 31 9 h5 21 - mad01_1 32 10 l6 22 - mad02_1 39 17 k6 29 - mad03_1 40 18 j6 30 - mad04_1 41 19 l7 31 - mad05_1 42 20 k7 32 - mad06_1 43 21 h6 33 - mad07_1 44 22 j7 34 - mad08_1 45 23 k8 35 - mad09_1 53 31 j10 43 - mad10_1 54 32 j8 44 - mad11_1 55 33 h10 45 - mad12_1 56 34 h9 46 - mad13_1 57 35 h7 47 - mad14_1 58 36 g10 48 - mad15_1 59 37 g9 49 - mad16_1 63 41 g8 53 - mad17_1 64 42 f10 54 - mad18_1 65 43 f9 55 - mad19_1 66 44 e11 56 - mad20_1 67 45 e10 - - mad21_1 68 46 f8 - - mad22_1 69 47 e9 - - mad23_1 70 48 d11 - - mad24_1 74 52 c10 60 -
document number: 002 - 04674 rev. *c page 29 of 116 mb9a310a series module pin name function pin no lqfp - 100 qfp - 100 bga - 1 12 lqfp - 80 lq fp - 64 qfn - 64 external bus mcsx0_1 external bus interface chip select output pin 88 66 a6 68 - mcsx1_1 87 65 d7 67 - mcsx2_1 86 64 c7 - - mcsx3_1 85 63 b7 - - mcsx4_1 83 61 d9 - - mcsx5_1 82 60 c8 - - mcsx6_1 79 57 b11 63 - mcsx7_1 77 55 a9 61 - mdqm0_1 external bus interface byte mask signal output 90 68 c6 70 - mdqm1_1 91 69 a5 71 - moex_1 external bus interface read enable signal for sram 94 72 c5 74 - mwex_1 external bus interface write enable signal for sram 93 71 d6 73 - madata00_1 external bus interface data bus 2 80 c1 2 - madata01_1 3 81 c2 3 - madata02_1 4 82 b3 4 - madata03_1 5 83 d1 5 - madata04_1 6 84 d2 6 - madata05_1 7 85 d3 7 - madata06_1 8 86 d5 8 - madata07_1 9 87 e1 9 - madata08_1 10 88 e2 10 - madata09_1 11 89 e3 11 - madata10_1 12 90 e4 12 - madata11_1 13 91 f1 - - madata12_1 14 92 f2 - - madata13_1 15 93 f3 - - madata14_1 16 94 g1 - - madata15_1 17 95 g2 - - male_1 address latch enable signal for multiplex 89 67 b6 69 - mrdy_1 external rdy input signal 96 74 c4 76 - mclkout_1 external bus clock output 84 62 a7 66 -
document number: 002 - 04674 rev. *c page 30 of 116 mb9a310a series module pin name function pin no lqfp - 100 qfp - 100 bga - 1 12 lqfp - 80 lq fp - 64 qfn - 64 external interrupt int00_0 external interrupt request 00 input pin 2 80 c1 2 2 int00_1 82 60 c8 - - int00_2 87 65 d7 67 54 int01_0 external interrupt request 01 input pin 3 81 c2 3 3 int01_1 83 61 d9 - - int02_0 external interrupt request 02 input pin 4 82 b3 4 4 int02_1 53 31 j10 43 35 int03_0 external interrupt request 03 input pin 93 71 d6 73 - int03_1 56 34 h9 46 38 int03_2 9 87 e1 9 5 int04_0 external interrupt request 04 input pin 12 90 e4 12 8 int04_1 59 37 g9 49 40 int04_2 10 88 e2 10 6 int05_0 external interrupt request 05 input pin 74 52 c10 60 - int05_1 65 43 f9 55 - int05_2 11 89 e3 11 7 int06_1 external interrupt request 06 input pin 73 51 c11 59 48 int06_2 45 23 k8 35 27 int07_2 external interrupt request 07 input pin 5 83 d1 5 - int08_1 external interrupt request 08 input pin 14 92 f2 - - int08_2 8 86 d5 8 - int09_1 external interrupt request 09 input pin 15 93 f3 - - int10_1 external interrupt request 10 input pin 16 94 g1 - - int11_1 external interrupt request 11 input pin 17 95 g2 - - int12_1 external interrupt request 12 input pin 27 5 j4 - - int13_1 external interrupt request 13 input pin 28 6 l5 - - int14_1 external interrupt request 14 input pin 39 17 k6 29 - int15_1 external interrupt request 15 input pin 96 74 c4 76 60 nmix non - maskable interrupt input 92 70 b5 72 57
document number: 002 - 04674 rev. *c page 31 of 116 mb9a310a series module pin name function pin no lqfp - 100 qfp - 100 bga - 1 12 lqfp - 80 lq fp - 64 qfn - 64 gpio p00 general - purpose i/o port 0 77 55 a9 61 49 p01 78 56 b9 62 50 p02 79 57 b11 63 51 p03 80 58 a8 64 52 p04 81 59 b8 65 53 p05 82 60 c8 - - p06 83 61 d9 - - p07 84 62 a7 66 - p08 85 63 b7 - - p09 86 64 c7 - - p0a 87 65 d7 67 54 p0b 88 66 a6 68 55 p0c 89 67 b6 69 56 p0d 90 68 c6 70 - p0e 91 69 a5 71 - p0f 92 70 b5 72 57 p10 general - purpose i/o port 1 52 30 j11 42 34 p11 53 31 j10 43 35 p12 54 32 j8 44 36 p13 55 33 h10 45 37 p14 56 34 h9 46 38 p15 57 35 h7 47 39 p16 58 36 g10 48 - p17 59 37 g9 49 40 p18 63 41 g8 53 44 p19 64 42 f10 54 45 p1a 65 43 f9 55 - p1b 66 44 e11 56 - p1c 67 45 e10 - - p1d 68 46 f8 - - p1e 69 47 e9 - - p1f 70 48 d11 - - p20 general - purpose i/o port 2 74 52 c10 60 - p21 73 51 c11 59 48 p22 72 50 e8 58 47 p23 71 49 d10 57 46
document number: 002 - 04674 rev. *c page 32 of 116 mb9a310a series module pin name function pin no lqfp - 100 qfp - 100 bga - 1 12 lqfp - 80 lq fp - 64 qfn - 64 gpio p30 general - purpose i/o port 3 9 87 e1 9 5 p31 10 88 e2 10 6 p32 11 89 e3 11 7 p33 12 90 e4 12 8 p34 13 91 f1 - - p35 14 92 f2 - - p36 15 93 f3 - - p37 16 94 g1 - - p38 17 95 g2 - - p39 18 96 f4 13 9 p3a 19 97 g3 14 10 p3b 20 98 h1 15 11 p3c 21 99 h2 16 12 p3d 22 100 g4 17 13 p3e 23 1 h3 18 14 p3f 24 2 j2 19 15 p40 general - purpose i/o port 4 27 5 j4 - - p41 28 6 l5 - - p42 29 7 k5 - - p43 30 8 j5 - - p44 31 9 h5 21 - p45 32 10 l6 22 - p46 36 14 l3 26 19 p47 37 15 k3 27 20 p48 39 17 k6 29 - p49 40 18 j6 30 22 p4a 41 19 l7 31 23 p4b 42 20 k7 32 24 p4c 43 21 h6 33 25 p4d 44 22 j7 34 26 p4e 45 23 k8 35 27 p50 general - purpose i/o port 5 2 80 c1 2 2 p51 3 81 c2 3 3 p52 4 82 b3 4 4 p53 5 83 d1 5 - p54 6 84 d2 6 - p55 7 85 d3 7 - p56 8 86 d5 8 - p60 general - purpose i/o port 6 96 74 c4 76 60 p61 95 73 b4 75 59 p62 94 72 c5 74 58 p63 93 71 d6 73 - p80 general - purpose i/o port 8 98 76 a3 78 62 p81 99 77 a2 79 63 pe0 general - purpose i/o port e 46 24 k9 36 28 pe2 48 26 l9 38 30 pe3 49 27 l10 39 31
document number: 002 - 04674 rev. *c page 33 of 116 mb9a310a series module pin name function pin no lqfp - 100 qfp - 100 bga - 1 12 lqfp - 80 lq fp - 64 qfn - 64 multi function serial 0 sin0_0 multifunction serial interface ch.0 input pin 73 51 c11 59 48 sin0_1 56 34 h9 46 - sot0_0 (sda0_0) multifunction serial interface ch.0 output pin this pin operates as sot0 when it is used in a uart/csio/lin (operation modes 0 to 3) and as sda0 when it is used in an i 2 c (operation mode 4). 72 50 e8 58 47 sot0_1 (sda0_1) 57 35 h7 47 - sck0_0 (scl0_0) multifunction serial interface ch.0 clock i/o pin this pin operates as sck0 when it is used in a csio (operation modes 2) and as scl0 when it is used in an i 2 c (operation mode 4). 71 49 d10 57 46 sck0_1 (scl0_1) 58 36 g10 48 - multi function serial 1 sin1_1 multifunction serial interface ch.1 input pin 53 31 j10 43 35 sot1_1 (sda1_1) multifunction serial interface ch.1 output pin this pin operates as sot1 when it is used in a uart/csio/lin (operation modes 0 to 3) and as sda1 when it is used in an i 2 c (operation mode 4). 54 32 j8 44 36 sck1_1 (scl1_1) multifunction serial interface ch.1 clock i/o pin this pin operates as sck1 when it is used in a csio (operation modes 2) and as scl1 when it is used in an i 2 c (operation mode 4). 55 33 h10 45 37 multi function serial 2 sin2_2 multifunction serial interface ch.2 input pin 59 37 g9 49 40 sot2_2 (sda2_2) multifunction serial interface ch.2 output pin this pin operates as sot2 when it is used in a uart/csio/lin (operation modes 0 to 3) and as sda2 when it is used in an i 2 c (operation mode 4). 63 41 g8 53 44 sck2_2 (scl2_2) multifunction serial interface ch.2 clock i/o pin this pin operates as sck2 when it is used in a csio (operation modes 2) and as scl2 when it is used in an i 2 c (operation mode 4). 64 42 f10 54 45 multi function serial 3 sin3_1 multifunction serial interface ch.3 input pin 2 80 c1 2 2 sin3_2 39 17 k6 29 - sot3_1 (sda3_1) multifunction serial interface ch.3 output pin this pin operates as sot3 when it is used in a uart/csio/lin (operation modes 0 to 3) and as sda3 when it is used in an i 2 c (operation mode 4). 3 81 c2 3 3 sot3_2 (sda3_2) 40 18 j6 30 - sck3_1 (scl3_1) multifunction serial interface ch.3 clock i/o pin this pin operates as sck3 when it is used in a csio (operation modes 2) and as scl3 when it is used in an i 2 c (operation mode 4). 4 82 b3 4 4 sck3_2 (scl3_2) 41 19 l7 31 -
document number: 002 - 04674 rev. *c page 34 of 116 mb9a310a series module pin name function pin no lqfp - 100 qfp - 100 bga - 1 12 lqfp - 80 lq fp - 64 qfn - 64 multi function serial 4 sin4_0 multifunction serial interface ch.4 input pin 87 65 d7 67 54 sin4_1 65 43 f9 55 - sin4_2 82 60 c8 - - sot4_0 (sda4_0) multifunction serial interface ch.4 output pin this pin operates as sot4 when it is used in a uart/csio/lin (operation modes 0 to 3) and as sda4 when it is used in an i 2 c (operation mode 4). 88 66 a6 68 55 sot4_1 (sda4_1) 66 44 e11 56 - sot4_2 (sda4_2) 83 61 d9 - - sck4_0 (scl4_0) multifunction serial interface ch.4 clock i/o pin this pin operates as sck4 when it is used in a csio (operation modes 2) and as scl4 when it is used in an i 2 c (operation mode 4). 89 67 b6 69 56 sck4_1 (scl4_1) 67 45 e10 - - sck4_2 (scl4_2) 84 62 a7 - - rts4_0 multifunction serial interface ch.4 rts output pin 90 68 c6 70 - rts4_1 69 47 e9 - - rts4_2 86 64 c7 - - cts4_0 multifunction serial interface ch.4 cts input pin 91 69 a5 71 - cts4_1 68 46 f8 - - cts4_2 85 63 b7 - - multi function serial 5 sin5_0 multifunction serial interface ch.5 input pin 96 74 c4 76 60 sin5_2 15 93 f3 - - sot5_0 (sda5_0) multifunction serial interface ch.5 output pin this pin operates as sot5 when it is used in a uart/csio/lin (operation modes 0 to 3) and as sda5 when it is used in an i 2 c (operation mode 4). 95 73 b4 75 59 sot5_2 (sda5_2) 16 94 g1 - - sck5_0 (scl5_0) multifunction serial interface ch.5 clock i/o pin this pin operates as sck5 when it is used in a csio (operation modes 2) and as scl5 when it is used in an i 2 c (operation mode 4). 94 72 c5 74 58 sck5_2 (scl5_2) 17 95 g2 - -
document number: 002 - 04674 rev. *c page 35 of 116 mb9a310a series module pin name function pin no lqfp - 100 qfp - 100 bga - 1 12 lqfp - 80 lq fp - 64 qfn - 64 multi function serial 6 sin6_0 multifunction serial interface ch.6 input pin 5 83 d1 5 - sin6_1 12 90 e4 12 8 sot6_0 (sda6_0) multifunction serial interface ch.6 output pin this pin operates as sot6 when it is used in a uart/csio/lin (operation modes 0 to 3) and as sda6 when it is used in an i 2 c (operation mode 4). 6 84 d2 6 - sot6_1 (sda6_1) 11 89 e3 11 7 sck6_0 (scl6_0) multifunction serial interface ch.6 clock i/o pin this pin operates as sck6 when it is used in a csio (operation modes 2) and as scl6 when it is used in an i 2 c (operation mode 4). 7 85 d3 7 - sck6_1 (scl6_1) 10 88 e2 10 6 multi function serial 7 sin7_1 multifunction serial interface ch.7 input pin 45 23 k8 35 27 sot7_1 (sda7_1) multifunction serial interface ch.7 output pin this pin operates as sot7 when it is used in a uart/csio/lin (operation modes 0 to 3) and as sda7 when it is used in an i 2 c (operation mode 4). 44 22 j7 34 26 sck7_1 (scl7_1) multifunction serial interface ch.7 clock i/o pin this pin operates as sck7 when it is used in a csio (operation modes 2) and as scl7 when it is used in an i 2 c (operation mode 4). 43 21 h6 33 25
document number: 002 - 04674 rev. *c page 36 of 116 mb9a310a series module pin name function pin no lqfp - 100 qfp - 100 bga - 1 12 lqfp - 80 lq fp - 64 qfn - 64 multi function timer 0 dtti0x_0 input signal of wave form generator to control outputs rto00 to rto05 of multi - function timer 0 18 96 f4 13 9 dtti0x_1 69 47 e9 - - frck0_0 16 - bit free - run timer ch.0 external clock input pin 13 91 f1 - - frck0_1 70 48 d11 - - frck0_2 53 31 j10 43 35 ic00_0 16 - bit input capture input pin of multi - function timer 0 icxx describes channel number. 17 95 g2 - - ic00_1 65 43 f9 55 - ic00_2 54 32 j8 44 36 ic01_0 16 94 g1 - - ic01_1 66 44 e11 56 - ic01_2 55 33 h10 45 37 ic02_0 15 93 f3 - - ic02_1 67 45 e10 - - ic02_2 56 34 h9 46 38 ic03_0 14 92 f2 - - ic03_1 68 46 f8 - - ic03_2 57 35 h7 47 39 rto00_0 (ppg00_0) wave form generator output of multi - function timer 0 this pin operates as ppg00 when it is used in ppg 0 output modes. 19 97 g3 14 10 rto00_1 (ppg00_1) 71 49 d10 - - rto01_0 (ppg00_0) wave form generator output of multi - function timer 0 this pin operates as ppg00 when it is used in ppg 0 output modes. 20 98 h1 15 11 rto02_0 (ppg02_0) wave form generator output of multi - function timer 0 this pin operates as ppg02 when it is used in ppg 0 output modes. 21 99 h2 16 12 rto03_0 (ppg02_0) wave form generator output of multi - function timer 0 this pin operates as ppg02 when it is used in ppg 0 output modes. 22 100 g4 17 13 rto04_0 (ppg04_0) wave form generator output of multi - function timer 0 this pin operates as ppg04 when it is used in ppg 0 output modes. 23 1 h3 18 14 rto05_0 (ppg04_0) wave form generator output of multi - function timer 0 this pin operates as ppg04 when it is used in ppg 0 output modes. 24 2 j2 19 15
document number: 002 - 04674 rev. *c page 37 of 116 mb9a310a series module pin name function pin no lqfp - 100 qfp - 100 bga - 1 12 lqfp - 80 lq fp - 64 qfn - 64 multi function timer 1 dtti1x_0 input signal of wave form generator to control outputs rto10 to rto15 of multi - function timer 1 8 86 d5 8 - dtti1x_1 39 17 k6 29 - frck1_0 16 - bit free - run timer ch.1 external clock input pin 87 65 d7 67 - frck1_1 44 22 j7 34 - ic10_0 16 - bit input capture input pin of multi - function timer 1 icxx describes channel number. 88 66 a6 68 - ic10_1 40 18 j6 30 - ic11_0 89 67 b6 69 - ic11_1 41 19 l7 31 - ic12_0 90 68 c6 70 - ic12_1 42 20 k7 32 - ic13_0 91 69 a5 71 - ic13_1 43 21 h6 33 - rto10_0 (ppg10_0) wave form generator output of multi - function timer 1 this pin operates as ppg10 when it is used in ppg 1 output modes. 2 80 c1 2 - rto10_1 (ppg10_1) 27 5 j4 - - rto11_0 (ppg10_0) wave form generator output of multi - function timer 1 this pin operates as ppg10 when it is used in ppg 1 output modes. 3 81 c2 3 - rto11_1 (ppg10_1) 28 6 l5 - - rto12_0 (ppg12_0) wave form generator output of multi - function timer 1 this pin operates as ppg12 when it is used in ppg 1 output modes. 4 82 b3 4 - rto12_1 (ppg12_1) 29 7 k5 - - rto13_0 (ppg12_0) wave form generator output of multi - function timer 1 this pin operates as ppg12 when it is used in ppg 1 output modes. 5 83 d1 5 - rto13_1 (ppg12_1) 30 8 j5 - - rto14_0 (ppg14_0) wave form generator output of multi - function timer 1 this pin operates as ppg14 when it is used in ppg 1 output modes. 6 84 d2 6 - rto14_1 (ppg14_1) 31 9 h5 21 - rto15_0 (ppg14_0) wave form generator output of multi - function timer 1 this pin operates as ppg14 when it is used in ppg 1 output modes. 7 85 d3 7 - rto15_1 (ppg14_1) 32 10 l6 22 -
document number: 002 - 04674 rev. *c page 38 of 116 mb9a310a series module pin name function pin no lqfp - 100 qfp - 100 bga - 1 12 lqfp - 80 lq fp - 64 qfn - 64 quadrature position/ revolution counter 0 ain0_0 qprc ch.0 ain input pin 9 87 e1 9 5 ain0_1 40 18 j6 30 22 ain0_2 2 80 c1 2 2 bin0_0 qprc ch.0 bin input pin 10 88 e2 10 6 bin0_1 41 19 l7 31 23 bin0_2 3 81 c2 3 3 zin0_0 qprc ch.0 zin input pin 11 89 e3 11 7 zin0_1 42 20 k7 32 24 zin0_2 4 82 b3 4 4 quadrature position/ revolution counter 1 ain1_1 qprc ch.1 ain input pin 74 52 c10 60 - ain1_2 43 21 h6 33 25 bin1_1 qprc ch.1 bin input pin 73 51 c11 59 - bin1_2 44 22 j7 34 26 zin1_1 qprc ch.1 zin input pin 72 50 e8 58 - zin1_2 45 23 k8 35 27 usb udm0 usb device / host d C pin 98 76 a3 78 62 udp0 usb device / host d + pin 99 77 a2 79 63 uhconx usb external pull - up control pin 95 73 b4 75 59
document number: 002 - 04674 rev. *c page 39 of 116 mb9a310a series module pin name function pin no lqfp - 100 qfp - 100 bga - 1 12 lqfp - 80 lq fp - 64 qfn - 64 r eset initx external reset input. a reset is valid when initx=l 38 16 k4 28 21 mode md0 mode 0 pin during normal operation, md0=l must be input. during serial programming to flash memory, md0=h must be input. 47 25 l8 37 29 md1 mode 1 pin during serial programming to flash memory, md1=l must be input. 46 24 k9 36 28 p ower vcc power supply pin 1 79 b1 1 1 vcc power supply pin 26 4 j1 - - vcc power supply pin 35 13 k1 25 18 vcc power supply pin 51 29 k11 41 33 vcc power supply pin 76 54 a10 - - usbvcc 3.3v power supply port for usb i/o 97 75 a4 77 61 gnd vss gnd pin - - b2 - - vss gnd pin 25 3 l1 20 16 vss gnd pin - - k2 - - vss gnd pin - - j3 - - vss gnd pin - - h4 - - vss gnd pin 34 12 l4 24 - vss gnd pin 50 28 l11 40 32 vss gnd pin - - k10 - - vss gnd pin - - j9 - - vss gnd pin - - h8 - - vss gnd pin - - b10 - - vss gnd pin - - c9 - - vss gnd pin 75 53 a11 - - vss gnd pin - - d8 - - vss gnd pin - - d4 - - vss gnd pin - - c3 - - vss gnd pin 100 78 a1 80 64 c lock x0 main clock (oscillation) input pin 48 26 l9 38 30 x0a sub clock (oscillation) input pin 36 14 l3 26 19 x1 main clock (oscillation) i/o pin 49 27 l10 39 31 x1a sub clock (oscillation) i/o pin 37 15 k3 27 20 crout_0 built - in high - speed cr - osc clock output port 74 52 c10 60 - crout_1 92 70 b5 72 57 analog p ower avcc a/d converter analog power supply pin 60 38 h11 50 41 avrh a/d converter analog reference voltage input pin 61 39 f11 51 42 analog gnd avss a/d converter gnd pin 62 40 g11 52 43 c pin c power stabilization capacity pin 33 11 l2 23 17 note: ? while this device contains a test access port (tap) based on the ieee 1149.1 - 2001 jtag standard, it is not fully compliant to all requirements of that standard. this device may contain a 32 - bit device id that is the same as the 32 - bit device id in other d evices with different functionality. the tap pins may also be configurable for purposes other than access to the tap controller.
document number: 002 - 04674 rev. *c page 40 of 116 mb9a310a series 5. i/o circuit type type circuit remarks a it is possible to select the main oscillation / gpio function when the main oscillation is selected. ? oscillation feedback resistor : approximately 1 m ? with standby mode control when the gpio is selected. ? cmos level output. ? cmos level hysteresis input ? with pull - up resistor control ? with standby mode control ? pull - up resistor : approximately 50 k ? i oh = - 4 ma, i ol = 4 ma b ? cmos level hysteresis input ? pull - up resistor : approximately 50 k p - ch p - ch n - ch r r p - ch p - ch n - ch x0 x1 pull - up resistor feedback resistor pull - up resistor pull - up resistor digital in put digital output digital output pull - up resistor control digital input standby mode control clock input standby mode control digital input standby mode control digital output digital output pull - up resistor control
document number: 002 - 04674 rev. *c page 41 of 116 mb9a310a series type circuit remarks c ? open drain output ? cmos level hysteresis input d it is possible to select the sub oscillation / gpio function when the sub oscillation is selected. ? oscillation feedback resistor : approximately 5 m ? with standby mode control when the gpio is selected. ? cmos level output. ? cmos level hysteresis input ? with pull - up resistor control ? wit h standby mode control ? pull - up resistor : approximately 50 k ? i oh = - 4 ma, i ol = 4 ma p - ch p - ch n - ch r r p - ch p - ch n - ch x0 a x1 a pull - up resistor feedback resistor pull - up resistor digital input digital out put digital output digital output pull - up resistor control digital input standby mode control clock input standby mode control digital input standby mode control digital output digital output pull - up resistor control n-ch
document number: 002 - 04674 rev. *c page 42 of 116 mb9a310a series type circuit remarks e ? cmos level output ? cmos level hysteresis input ? with pull - up resistor control ? with standby mode control ? pull - up resistor : approximately 50 k ? i oh = - 4 ma, i ol = 4 ma ? when this pin is used as an i 2 c pin, the digital output p - ch transistor is always off ? +b input is available f ? cmos level output ? cmos level hysteresis input ? with input control ? analog input ? with pull - up resistor control ? with standby mode control ? pull - up resistor : approximately 50 k ? i oh = - 4 ma, i ol = 4 ma ? when this pin is used as an i 2 c pin, the digital output p - ch transistor is always off ? +b input is available standby mode control digital output pull - up resistor control digital output digital input p - ch p - ch n - ch digital output digital output pull - up resistor control input control standby mode control analog input digital input p - ch p - ch n - ch r r
document number: 002 - 04674 rev. *c page 43 of 116 mb9a310a series type circuit remarks g ? cmos level output ? cmos level hysteresis input ? with pull - up resistor control ? with standby mode control ? pull - up resistor : approximately 50 k ? i oh = - 12 ma, i ol = 12 ma ? +b input is available h ? it is possible to select the usb io / gpio function. when the usb io is selected. ? full - speed, low - speed control when the gpio is selected. ? cmos level output ? cmos level hysteresis input ? with standby mode control ? i oh = - 20.5 ma, i ol = 18.5 ma standby mode control digital output pull - up resistor control digital output digital input p - ch p - ch n - ch r differential differential input udp(+)input udm(-)input usb/gpio select gpio digital input gpio digital input gpio digital input circuit control gpio digital input/output direction gpio digital output usb input/output direction udm(-)output udp(+)output usb full-speed, low-speed control gpio digital input circuit control gpio digital input/output direction gpio digital output ebp ebm
document number: 002 - 04674 rev. *c page 44 of 116 mb9a310a series type circuit remarks i ? cmos level output ? cmos level hysteresis input ? 5v tolerant ? with standby mode control ? i oh = - 4 ma, i ol = 4 ma ? when this pin is used as an i 2 c pin, the digital output p - ch transistor is always off j cmos level hysteresis input digital in put standby mode control digital output digital output r p-ch n-ch mode input
document number: 002 - 04674 rev. *c page 45 of 116 mb9a310a series 6. handling precautions any semiconductor devices have inherently a certain rate of failure. the possibility of failure is greatly affected by the co nditions in which they are used (circuit conditions, environmental conditions, etc.). this page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your cypress semiconductor devices. 6.1 precautions for product design this section describes precautions when designing electronic equipment using semiconductor devices. absolute maximum ratings semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. do not exceed these ratings. recommended operating co nditions recommended operating conditions are normal operating ranges for the semiconductor device. all the device's electrical characteristics are warranted when operated within these ranges. always use semiconductor devices within the recommended operati ng conditions. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering applicat ion outside the listed conditions are advised to contact their sales representative beforehand. processing and protection of pins these precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/outpu t functions. 1. preventing over - voltage and over - current conditions exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the dev ice , and in extreme cases leads to permanent damage of the device. try to prevent such overvoltage or over - current conditions at the design stage. 2. protection of output pins shorting of output pins to supply pins or other output pins, or connection to large cap acitance can cause large current flows. such conditions if present for extended periods of time can damage the device. therefore, avoid this type of connection. 3. handling of unused input pins unconnected input pins with very high impedance levels can advers ely affect stability of operation. such pins should be connected through an appropriate resistance to a power supply pin or ground pin. latch - up semiconductor devices are constructed by the formation of p - type and n - type areas on a substrate. when subjecte d to abnorma l ly high voltages, internal parasitic pnpn junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred ma to flow continuously at the power supply pin. this condition is called latch - up. caut ion: the occurrence of latch - up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. to prevent this from happening, do the following: 1. be sure that voltages applied to pins do not e xceed the absolute maximum ratings. this should include attention to abnormal noise, surge levels, etc. 2. be sure that abnormal current flows do not occur during the power - on sequence. observance of safety regulations and standards most countries in the worl d have established standards and regulations regarding safety, protection from electromagnetic interference, etc. customers are requested to observe applicable regulations and standards in the design of products. fail - safe design any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over - current level s and other abnormal operating conditions.
document number: 002 - 04674 rev. *c page 46 of 116 mb9a310a series precautions related to usage of devices cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may direct ly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. 6.2 precautions for package mounting package mounting may be either lead insertion type or surface mount type. in either case, for heat resistance during solderin g, you should only mount under cypress recommended conditions. for detailed information about mount conditions, contact your sales representative. lead insertion type mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the boar d, or mounting by using a socket. direct mounting onto boards normally involves processes for i nserting leads into through - holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. in this case, the soldering process usually causes leads to be s ubjected to thermal stress in excess of the absolute ratings for storage temperature. mounting processes should conform to cypress recommended mounting conditions. if socket mounting is used, differences in surface treatment of the socket contacts and ic lead surfaces can lead to contact deterioration after long periods . for this reason it is recommended that the surface treatment of socket contacts and ic leads be verified before mounting. surface mount type surface mount packaging has longer and thinner leads than lead - insertion packaging, and therefore leads are more easily deformed or bent. the use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connec tions caused by deformed pins, or shorting due to solder bridges. you must use appropriate mounting techniques. cyp ress recommends the solder reflow method, and has established a ranking of mounting conditions for each product. users are advised to mount packages in accordance with cypress ranking of recommended conditions. lead - free packaging caution: when ball grid a rray (bga) packages with sn - ag - cu balls are mounted using sn - pb eutectic soldering, junction strength may be reduced under some conditions of use. storage of semiconductor devices because plastic chip packages are formed from plastic resins, exposure to na tural environmental conditions will cause absorption of moisture. during mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reduci ng moisture resistance and causing packages to crack. to prevent, do the fo llowing: 1. avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. store products in locations where temperature changes are slight. 2. use dry boxes for product storage. products should be stored below 70% relative hum idity, and at temperatures between 5 c and 30 c . when you open dry package that recommends humidity 40% to 70% relative humidity. 3. when necessary, cypress packages semiconductor devices in highly moisture - resistant aluminum laminate bags, with a silica gel desiccant. devices should be sealed in their aluminum laminate bags for storage. 4. avoid storing packages where they are exposed to corrosive gases or high levels of dust.
document number: 002 - 04674 rev. *c page 47 of 116 mb9a310a series baking packages that have absorbed moisture may be de - moisturized by baking (heat d rying). follow the cypress recommended conditions for baking. condition: 125 c /24 h static electricity because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following preca utions: 1. maintain relative humidity in the working environment between 40% and 70%. use of an apparatus for ion generation may be needed to remove electricity. 2. electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. 3. eliminate static body electric ity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 m ). wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. 4. ground all fixtures and instruments, or protect with anti - static measures. 5. avoid the use of styrofoam or other highly static - prone materials for storage of completed board assemblies. 6.3 precautions for use environment reliability of semiconductor devices depends on ambient te mperature and other conditions as described above. for reliable performance, do the following: 1. humidity prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. if high humidity levels are anticipated, consider anti - humidity processing. 2. discharge of static electricity when high - voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. in such cases, use anti - static measures or processing to prevent discharges. 3. corrosive gases, dust , or oil exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. if you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. 4. radiation, inclu ding cosmic radiation most devices are not designed for environments involving exposure to radiation or cosmic radiation. users should provide shielding as appropriate. 5. smoke, flame caution: plastic molded devices are flammable, and therefore should not be used near combustible substances. if devices begin to smoke or burn, there is danger of the release of toxic gases. customers considering the use of cypress products in other special environmental conditions should consult with sales representatives.
document number: 002 - 04674 rev. *c page 48 of 116 mb9a310a series 7. handling devices power supply pins in products with multiple v cc and v ss pins, respective pins at the same potential are interconnected within the device in order to prevent malfunctions such as latch - up. however, all of these pins should be connected exte rnally to the power supply or ground lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. moreover, connect the current supply source with each power supply pin and gnd pin of this device at low impedance. it is also advisable that a ceramic capacitor of approximately 0.1 f be connected as a bypass capacitor between each power supply pin a nd gnd pin , between avcc p in and avss pin near this device. stabilizing power supply voltage a malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the recommende d operating conditions of the vcc power supply voltage. as a rul e, with voltage stabilization, suppress the voltage fluctuation so that the fluctuation in vcc ripple (peak - to - peak value) at the commercial frequency (50 hz/60 hz) does not exceed 10% of the vcc value in the recommended operating conditions, and the trans ient fluctuation rate does not exceed 0.1 v/s when there is a momentary fluctuation on switching the power supply. crystal oscillator circuit noise near the x0/x1 and x0a/x1a pins may cause the device to malfunction. design the printed circuit board so th at x0/x1, x0a/x1a pins, the crystal oscillator, and the bypass capacitor to ground are located as close to the device as possible. it is strongly recommended that the pc board artwork be designed such that the x0/x1 and x0a/x1a pins are surrounded by groun d plane as this is expected to produce stable operation. evaluate oscillation of your using crystal oscillator by your mount board. using an external clock when using an external clock, the clock signal should be driven to the x0,x0a pin only and the x1,x1 a pin should be kept open. handling when using multi - function serial pin as i 2 c pin if it is using the multi function serial pin as i 2 c pins, p - ch transistor of digital output is always disabled. however, i 2 c pins need to keep the electrical characteristic like other pins and not to connect to the external i 2 c bus system with power off. ? example of using an external clock device x0(x0a) x1(x1a) open
document number: 002 - 04674 rev. *c page 49 of 116 mb9a310a series c pin this series contains the regulator. be sure to connect a smoothing capacitor (c s ) f or the regulator between the c pin and the gnd pin. please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor. however, some laminated ceramic capacitors have the characteristics of capacitance variatio n due to thermal fluctuation (f characteristics and y5v characteristics). please select the capacitor that meets the specifications in the operating conditio ns to use by evaluating the temperature characteristics of a capacitor. a smoothing capacitor of ab out 4.7 f would be recommended for this series. mode pins (md0) connect the md pin (md0) directly to v cc or v ss pins. design the printed circuit board such that the pull - up/down resistor stays low, as well as the distance between the mode pins and v cc pins or v ss pins is as short as possible and the connection impedance is low, when the pins are pulled - up/down such as for switching the pin level and rewriting the flash memory data. it is because of preventing the device erroneously switching to test mode due to noise. notes on power - on turn power on/off in the following order or at the same time. if not using the a/d converter, connect avcc = vcc and avss = vss. turning on: vcc serial communication there is a possibility to receive wrong data due to the noise or other causes on the serial communication. therefore, design a printed circuit board so as to avoid noise. consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the end. if an error is detected, retransmit the data. differences in features among the products with different memory sizes and between flash products and mask products the electric characteristics including power consumption, esd, latch - up, noise characteristics, and oscillation characteristics among the products with different memory sizes and between flash products and mask products are different beca use chip layout and memory structures are different. if you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics . device c vss c s gnd
document number: 002 - 04674 rev. *c page 50 of 116 mb9a310a series 8. block diagram *1: for the mb9af311la/ma, f312la/ma, mb9af314la/ma, mb 9af315ma and mb9af316ma, etm is not available. * 2 : for the mb9af311la, f312la and mb9af314la, the external bus interface and 12 - bit a/d converter (unit 2) are not available. and the multi - function serial interface does not support hardware flow control in these products. a h b - a p b b r i d g e : a p b 1 ( m a x 4 0 m h z ) f l a s h i / f c o r t e x - m 3 c o r e @ 4 0 m h z ( m a x ) c l o c k r e s e t g e n e r a t o r d u a l - t i m e r w a t c h d o g t i m e r ( h a r d w a r e ) d m a c 8 c h m u l t i - f u n c t i o n t i m e r x 2 m u l t i - f u n c t i o n s e r i a l i / f 8 c h . ( w i t h f i f o c h . 4 t o 7 ) & h w f l o w c o n t r o l ( c h . 4 ) * 2 1 6 - b i t f r e e - r u n t i m e r 3 c h . 1 6 - b i t o u t p u t c o m p a r e 6 c h . 1 6 - b i t i n p u t c a p t u r e 4 c h . w a v e f o r m g e n e r a t o r 3 c h . a / d a c t i v a t i o n c o m p a r e 3 c h . 1 6 - b i t p p g 3 c h . w a t c h c o u n t e r u n i t 0 g p i o c s v l v d e x t e r n a l i n t e r r u p t c o n t r o l l e r 1 6 - p i n + n m i p o w e r - o n r e s e t t p i u * 1 r o m t a b l e e t m * 1 s r a m 0 8 / 1 6 k b y t e s w j - d p s r a m 1 8 / 1 6 k b y t e i d s y s m b 9 a f 3 1 1 l a / m a / n a , f 3 1 2 l a / m a / n a , f 3 1 4 l a / m a / n a , f 3 1 5 m a / n a , f 3 1 6 m a / n a b a s e t i m e r 1 6 - b i t 8 c h . / 3 2 - b i t 4 c h . n v i c w a t c h d o g t i m e r ( s o f t w a r e ) s e c u r i t y 1 2 - b i t a / d c o n v e r t e r x 3 u n i t 1 u n i t 2 * 2 t r s t x , t c k , t d i , t m s t r a c e d [ 3 : 0 ] , t r a c e c l k a n [ 1 5 : 0 ] t i o a [ 7 : 0 ] t i o b [ 7 : 0 ] i c 0 [ 3 : 0 ] d t t i [ 1 : 0 ] x r t o 0 [ 5 : 0 ] f r c k [ 1 : 0 ] c t d o s c k [ 7 : 0 ] s i n [ 7 : 0 ] s o t [ 7 : 0 ] i n t [ 1 5 : 0 ] n m i x p 0 [ f : 0 ] , p 1 [ f : 0 ] , . . . p x [ x : 0 ] i n i t x m o d e - c t r l i r q - m o n i t o r p i n - f u n c t i o n - c t r l m d [ 1 : 0 ] r e g u l a t o r q p r c 2 c h . a i n [ 1 : 0 ] b i n [ 1 : 0 ] z i n [ 1 : 0 ] l v d c t r l c r c a c c e l e r a t o r i c 1 [ 3 : 0 ] a d t g x r t s 4 c t s 4 e x t e r n a l b u s i / f * 2 m a d [ 2 4 : 0 ] m a d a t a [ 1 5 : 0 ] m c s x [ 7 : 0 ] , m o e x , m w e x , m a l e , m r d y , m c l k o u t , m d q m [ 1 : 0 ] r t o 1 [ 5 : 0 ] o n - c h i p f l a s h 6 4 / 1 2 8 / 2 5 6 / 3 8 4 / 5 1 2 k b y t e u s b 2 . 0 ( h o s t / f u n c ) p h y u s b v c c u d p 0 / u d m 0 u h c o n x a h b - a h b b r i d g e a h b - a p b b r i d g e : a p b 0 ( m a x 4 0 m h z ) m u l t i - l a y e r a h b ( m a x 4 0 m h z ) a h b - a p b b r i d g e : a p b 2 ( m a x 4 0 m h z ) x 0 x 1 x 0 a p l l c l k c r 1 0 0 k h z s o u r c e c l o c k c r o u t m a i n o s c s u b o s c c r 4 m h z a v c c , a v s s , a v r h u s b c l o c k c t r l p l l
document number: 002 - 04674 rev. *c page 51 of 116 mb9a310a series 9. memory size see memory size in 1 . p roduct l ineup to confirm the memory size. 10. memory map memory map (1) peripherals area 0x41ff_ffff 0xffff_ffff 0xe010_0000 0x4006_1000 0xe000_0000 0x4006_0000 dmac 0x4005_0000 reserved 0x4004_0000 usb ch.0 0x4003_f000 ext-bus i/f 0x4003_b000 0x4003_a000 watch counter 0x7000_0000 0x4003_9000 crc 0x4003_8000 mfs 0x6000_0000 0x4003_7000 reserved 0x4003_6000 usb clock ctrl 0x4003_5000 lvd 0x4400_0000 0x4003_4000 0x4200_0000 0x4003_3000 gpio 0x4003_2000 reserved 0x4000_0000 0x4003_1000 int-req.read 0x4003_0000 exti 0x4002_f000 reserved 0x2400_0000 0x4002_e000 cr trim 0x2200_0000 0x4002_8000 0x4002_7000 a/dc 0x4002_6000 qprc 0x2008_0000 0x4002_5000 base timer 0x2000_0000 sram1 ppg 0x1ff8_0000 sram0 0x4002_2000 0x0010_2000 0x4002_1000 mft unit1 0x0010_0000 security/cr trim 0x4002_0000 mft unit0 0x4001_6000 0x4001_5000 dual timer 0x4001_3000 0x0000_0000 0x4001_2000 sw wdt 0x4001_1000 hw wdt 0x4001_0000 clock/reset 0x4000_1000 0x4000_0000 flash i/f reserved reserved 32mbytes bit band alias reserved reserved cortex-m3 private peripherals reserved reserved external device area see the next page "nmemory map (2),(3)" for the memory size details. reserved reserved flash reserved reserved peripherals reserved 32mbytes bit band alias reserved reserved
document number: 002 - 04674 rev. *c page 52 of 116 mb9a310a series memory map (2) see " mb9 a310 /1 1 0 series flash programming m anual " for sector s tructure of flash. mb9af316ma/na mb9af315ma/na mb9af314la/ma/na 0x2008_0000 0x2008_0000 0x2008_0000 0x2000_4000 0x2000_4000 0x2000_4000 0x2000_0000 0x2000_0000 0x2000_0000 0x1fff_c000 0x1fff_c000 0x1fff_c000 0x0010_2000 0x0010_2000 0x0010_2000 0x0010_1000 cr trimming 0x0010_1000 cr trimming 0x0010_1000 cr trimming 0x0010_0000 security 0x0010_0000 security 0x0010_0000 security 0x0008_0000 0x0006_0000 0x0004_0000 0x0000_0000 sa4-7(8kbx4) 0x0000_0000 sa4-7(8kbx4) 0x0000_0000 sa4-7(8kbx4) reserved sram0 16kbytes sram1 16kbytes reserved sram1 16kbytes sram0 16kbytes reserved reserved reserved reserved flash 512kbytes reserved sram1 16kbytes sram0 16kbytes reserved reserved flash 256kbytes sa10-15(64kbx6) sa10-13(64kbx4) sa10-11(64kbx2) sa8-9(48kbx2) sa8-9(48kbx2) sa8-9(48kbx2) flash 384kbytes
document number: 002 - 04674 rev. *c page 53 of 116 mb9a310a series memory map (3) see " mb9 a310a /1 1 0 a series flash programming m anual " for sector s tructure of flash. mb9af312la/ma/na mb9af311la/ma/na 0x2008_0000 0x2008_0000 0x2000_2000 0x2000_2000 0x2000_0000 0x2000_0000 0x1fff_e000 0x1fff_e000 0x0010_2000 0x0010_2000 0x0010_1000 cr trimming 0x0010_1000 cr trimming 0x0010_0000 security 0x0010_0000 security 0x0002_0000 0x0001_0000 0x0000_0000 sa4-7(8kbx4) 0x0000_0000 sa4-7(8kbx4) reserved sram1 8kbytes reserved sram1 8kbytes reserved reserved sa8-9(16kbx2) flash 128kbytes sram0 8kbytes sram0 8kbytes flash 64kbytes sa8-9(48kbx2) reserved reserved
document number: 002 - 04674 rev. *c page 54 of 116 mb9a310a series peripheral address map start address end address bus peripherals 0x4000_0000 h 0x4000_0fff h ahb flash memory i/f register 0x4000_1000 h 0x4000_ffff h reserved 0x4001_0000 h 0x4001_0fff h apb0 clock/reset control 0x4001_1000 h 0x4001_1fff h hardware watchdog timer 0x4001_2000 h 0x4001_2fff h software watchdog timer 0x4001_3000 h 0x4001_4fff h reserved 0x4001_5000 h 0x4001_5fff h dual - timer 0x4001_6000 h 0x4001_ffff h reserved 0x4002_0000 h 0x4002_0fff h apb1 multi - function timer unit0 0x4002_1000 h 0x4002_1fff h multi - function timer unit1 0x4002_2000 h 0x4002_3fff h reserved 0x4002_4000 h 0x4002_4fff h ppg 0x4002_5000 h 0x4002_5fff h base timer 0x4002_6000 h 0x4002_6fff h quadrature position/revolution counter 0x4002_7000 h 0x4002_7fff h a/d converter 0x4002_8000 h 0x4002_dfff h reserved 0x4002_e000 h 0x4002_efff h built - in cr trimming 0x4002_f000 h 0x4002_ffff h reserved 0x4003_0000 h 0x4003_0fff h apb2 external interrupt controller 0x4003_1000 h 0x4003_1fff h interrupt source check register 0x4003_2000 h 0x4003_2fff h reserved 0x4003_3000 h 0x4003_3fff h gpio 0x4003_4000 h 0x4003_4fff h reserved 0x4003_5000 h 0x4003_5fff h low - voltage detector 0x4003_6000 h 0x4003_6fff h usb clock generator 0x4003_7000 h 0x4003_7fff h reserved 0x4003_8000 h 0x4003_8fff h multi - function serial 0x4003_9000 h 0x4003_9fff h crc 0x4003_a000 h 0x4003_afff h watch counter 0x4003_b000 h 0x4003_efff h reserved 0x4003_f000 h 0x4003_ffff h external bus interface 0x4004_0000 h 0x4004_ffff h ahb usb ch.0 0x4005_0000 h 0x4005_ffff h reserved 0x4006_0000 h 0x4006_0fff h dmac register 0x4006_1000 h 0x4006_1fff h reserved 0x4006_2000 h 0x4006_2fff h reserved 0x4006_3000 h 0x4006_3fff h reserved 0x4006_4000 h 0x41ff_ffff h reserved
document number: 002 - 04674 rev. *c page 55 of 116 mb9a310a series 11. pin status i n each cpu state the terms used for pin status have the following meanings. ? initx=0 this is the period when the initx pin is the "l" level. ? initx=1 this is the period when the initx pin is the "h" level. ? spl=0 this is the status that the standby pin level setting bit (spl) in the standby mode control register (stb_ctl) is set to "0". ? spl=1 this i s the status that the standby pin level setting bit (spl) in the standby mode control register (stb_ctl) is set to "1". ? input enabled indicates that the input function can be used. ? internal input fixed at "0" this is the status that the input function cann ot be used. internal input is fixed at "l". ? hi - z indicates that the pin drive transistor is disabled and the pin is put in the hi - z state. ? setting disabled indicates that the setting is disabled. ? maintain previous state maintains the state that was immedia tely prior to entering the current mode. if a built - in peripheral function is operating, the output follows the peripheral function. if the pin is being used as a port, that output is maintained. ? analog input is enabled indicates that the analog input is e nabled. ? trace output indicates that the trace function can be used.
document number: 002 - 04674 rev. *c page 56 of 116 mb9a310a series list of pin status pin status type function group power - on reset or low voltage detection state initx input state device internal reset state run mode or sleep mode state timer mode or stop mode state power supply unstable power supply stable power supply stable power supply stable - initx=0 initx=1 initx=1 initx=1 - - - - spl=0 spl=1 a gpio selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z/ internal input fixed at "0" main crystal oscillator input pin input enabled input enabled input enabled input enabled input enabled input enabled b gpio selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z/ internal input fixed at "0" main crystal oscillator output pin hi - z/ internal input fixed at "0"/ or input enabled hi - z/ internal input fixed at "0" hi - z/ internal input fixed at "0" maintain previous state maintain previous state/ hi - z at oscillation stop* 1 / internal input fixed at "0" maintain previous state/ hi - z at oscillation stop* 1 / internal input fixed at "0" c initx input pin pull - up/ input enabled pull - up/ input enabled pull - up/ input enabled pull - up/ input enabled pull - up/ input enabled pull - up/ input enabled d mode input pin input enabled input enabled input enabled input enabled input enabled input enabled e jtag selected hi - z pull - up/ input enabled pull - up/ input enabled maintain previous state maintain previous state maintain previous state gpio selected setting disabled setting disabled setting disabled hi - z/ internal input fixed at "0" f trace selected setting disabled setting disabled setting disabled maintain previous state maintain previous state trace output external interrupt enabled selected maintain previous state gpio selected, or resource other than above selected hi - z hi - z/ input enabled hi - z/ input enabled hi - z/ internal input fixed at "0" g trace selected setting disabled setting disabled setting disabled maintain previous state maintain previous state trace output gpio selected, or resource other than above selected hi - z hi - z/ input enabled hi - z/ input enabled hi - z/ internal input fixed at " 0 "
document number: 002 - 04674 rev. *c page 57 of 116 mb9a310a series pin status type function group power - on reset or low voltage detection state initx input state device internal reset state run mode or sleep mode state timer mode or stop mode state power supply unstable power supply stable power supply stable power supply stable - initx=0 initx=1 initx=1 initx=1 - - - - spl=0 spl=1 h external interrupt enabled selected setting disabled setting disabled setting disabled maintain previous state maintain previous state maintain previous state gpio selected, or resource other than above selected hi - z hi - z/ input enabled hi - z/ input enabled hi - z/ internal input fixed at "0" i gpio selected, resource selected hi - z hi - z/ input enabled hi - z/ input enabled maintain previous state maintain previous state hi - z/ internal input fixed at "0" j nmix selected setting disabled setting disabled setting disabled maintain previous state maintain previous state maintain previous state gpio selected, or resource other than above selected hi - z hi - z/ input enabled hi - z/ input enabled hi - z/ internal input fixed at "0" k analog input selected hi - z hi - z/ internal input fixed at "0"/ analog input enabled hi - z/ internal input fixed at "0"/ analog input enabled hi - z/ internal input fixed at "0"/ analog input enabled hi - z/ internal input fixed at "0"/ analog input enabled hi - z/ internal input fixed at "0"/ analog input enabled gpio selected, or resource other than above selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z/ internal input fixed at "0" l external interrupt enabled selected setting disabled setting disabled setting disabled maintain previous state maintain previous state maintain previous state analog input selected hi - z hi - z/ internal input fixed at "0"/ analog input enabled hi - z/ internal input fixed at "0"/ analog input enabled hi - z/ internal input fixed at "0"/ analog input enabled hi - z/ internal input fixed at "0"/ analog input enabled hi - z/ internal input fixed at "0"/ analog input enabled gpio selected, or resource other than above selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z/ internal input fixed at "0" m gpio selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z/ internal input fixed at "0" sub crystal oscillator input pin input enabled input enabled input enabled input enabled input enabled input enabled
document number: 002 - 04674 rev. *c page 58 of 116 mb9a310a series pin status type function group power - on reset or low voltage detection type initx input state device internal reset state run mode or sleep mode state timer mode or stop mode state power supply unstable power supply stable power supply stable power supply stable - initx=0 initx=1 initx=1 initx=1 - - - - spl=0 spl=1 n gpio selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z/ internal input fixed at " 0 " sub crystal oscillator output pin hi - z/ internal input fixed at " 0 " / or input enabled hi - z/ internal input fixed at " 0 " hi - z/ internal input fixed at " 0 " maintain previous state maintain previous state/ hi - z at oscillation stop* 2 / internal input fixed at " 0 " maintain previous state/ hi - z at oscillation stop* 2 / internal input fixed at " 0 " o gpio selected hi - z hi - z/ input enabled hi - z/ input enabled maintain previous state maintain previous state hi - z/ internal input fixed at " 0 " usb i/o pin setting disabled setting disabled setting disabled maintain previous state hi - z at transmission/ input enabled/ internal input fixed at " 0 " at reception hi - z at transmission/ input enabled/ internal input fixed at " 0 " at reception p mode input pin input enabled input enabled input enabled input enabled input enabled input enabled gpio selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z/input enabled *1 : oscillation is stopped at sub timer mode, low speed cr timer mode, and stop mode. *2 : oscillation is stopped at stop mode.
document number: 002 - 04674 rev. *c page 59 of 116 mb9a310a series 12. electrical characteristics 12.1 absolute maximum ratings parameter symbol rating unit remarks min max power supply voltage* 1, * 2 vcc vss - 0.5 vss + 6.5 v power supply voltage (for usb) * 1, * 3 usbvcc vss - 0.5 vss + 6.5 v analog power supply voltage* 1, * 4 avcc vss - 0.5 vss + 6.5 v analog reference voltage* 1, * 4 avrh vss - 0.5 vss + 6.5 v input voltage* 1 v i vss - 0.5 vcc + 0.5 ( 6.5v) v except for usb pin vss - 0.5 usbvcc + 0.5 ( 6.5 v) v usb pin vss - 0.5 vss + 6.5 v 5v tolerant analog pin input voltage* 1 v ia vss - 0.5 avcc + 0.5 ( 6.5 v) v output voltage* 1 v o vss - 0.5 vcc + 0.5 ( 6.5 v) v clamp maximum current i clamp - 2 +2 ma *8 clamp total maximum current [i clamp ] +20 ma *8 "l" level maximum output current* 5 i ol - 10 ma 4ma type 20 ma 12ma type 39 ma p80, p81 "l" level average output current* 6 i olav - 4 ma 4ma type 12 ma 12ma type 18.5 ma p80, p81 "l" level total maximum output current i ol - 100 ma "l" level total average output current* 7 i olav - 50 ma "h" level maximum output current* 5 i oh - - 10 ma 4ma type - 20 ma 12ma type - 39 ma p80, p81 "h" level average output current* 6 i ohav - - 4 ma 4ma type - 12 ma 12ma type - 20.5 ma p80, p81 "h" level total maximum output current i oh - - 100 ma "h" level total average output current* 7 i ohav - - 50 ma power consumption p d - 300 mw storage temperature t stg - 55 + 150 c *1: these parameters are based on the condition that vss = avss = 0.0 v. *2 : vcc must not drop below vss - 0.5 v. *3 : usbvcc must not drop below vss - 0.5 v. * 4 : be careful not to exceed vcc + 0.5 v, for example, when the power is turned on. * 5 : the maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins. * 6 : the average output current is defined as the average current value flowing through any one of the corresponding pins for a 100 ms period. * 7 : the total average output current is defined as the average current value flowi ng through all of corresponding pins for a 100 ms.
document number: 002 - 04674 rev. *c page 60 of 116 mb9a310a series *8 : ? see 4 . list of pin functions and 5 . i/o circuit type ab out +b input available pin. ? use within recommended operating conditions. ? use at dc voltage (current) the +b input . ? the +b signal should always be applied a limiting resistance placed between the +b signal and the device. ? the value of the limiting resistance should be set so that when the +b signal is applied the input current to the device pin does not exceed rated values, either instantaneously or for prolonged periods. ? note that when the device drive current is low, such as in the low - power consumption modes, the +b input potential may pass through the protective diode and increase the potential at the v cc and avcc pin, and this may affect other devices. ? note that if a +b signal is input when the device power supply is o ff (not fixed at 0 v), the power supply is provided from the pins, so that incomplete operation may result. ? the following is a r ecommended circuit example (i/o equivalent circuit ) . warning : ? semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. r +b input (0v to 16v) p - ch v cc v cc limiting resistor n - ch av cc analog input digital input digital output protection diode
document number: 002 - 04674 rev. *c page 61 of 116 mb9a310a series 12.2 recommended operating conditions (v ss = av ss = 0.0v) parameter symbol conditions value unit remarks min max power supply voltage vcc - 2.7 * 4 5.5 v power supply voltage (3v power supply) for usb usbvcc 3.0 3.6 ( vcc) v *1 2.7 5.5 ( vcc) *2 analog power supply voltage avcc - 2.7 5.5 v avcc = vcc analog reference voltage avrh - 2.7 avcc v smoothing capacitor c s - 1 10 f for built - in regulator* 3 operating temperature lqi100 lqh080 lqd064 lqg064 vnc064 lbc112 t a - - 40 + 105 c pqh100 t a when mounted on four - layer pcb - 40 + 105 c when mounted on double - sided single - layer pcb - 40 + 105 c icc 35ma - 40 + 85 c icc > 35ma *1 : when p81/udp0 and p80/udm0 pin are used as usb (udp0, udm0). *2 : when p81/udp0 and p80/udm0 pin are used as gpio (p81, p80). * 3 : see "c pin" in " 7 . handling devices " for the connection of the smoothing capacitor. * 4 : in between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage or more, instruction execution and low voltage detection function by built - in high - speed cr (including main pll is used) or built - in low - speed cr is possible to operate only. warning : ? the recommended operating conditions are required in order to ensure the normal operation of the semicondu ctor device. all of the device's electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely af fect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their representatives beforehand.
document number: 002 - 04674 rev. *c page 62 of 116 mb9a310a series 12.3 dc characteristics 12.3.1 current r ating (vcc = avcc = 2.7v to 5.5v, usbvcc = 3.0v to 3.6v, vss = avss = 0v, t a = - 40 c to + 105 c ) parameter symbol pin name conditions value unit remarks typ * 3 max * 4 run mode current icc vcc pll run mode cpu: 40 mhz, peripheral: 40 mhz, flash 0 wait frwtr.rwt = 00 fsyndn.sd = 000 *5 32 41 ma *1 cpu: 40 mhz, peripheral: 40 mhz, flash 3 wait frwtr.rwt = 00 fsyndn.sd = 011 *5 21 28 ma *1 high - speed cr run mode cpu/ peripheral: 4 mhz * 2 flash 0 wait frwtr.rwt = 00 fsyndn.sd = 000 3.9 7.7 ma *1 sub run mode cpu/ peripheral: 32 khz flash 0 wait frwtr.rwt = 00 fsyndn.sd = 000 *6 0.15 3.2 ma *1 low - speed cr run mode cpu/ peripheral: 100 khz flash 0 wait frwtr.rwt = 00 fsyndn.sd = 000 0.2 3.3 ma *1 sleep mode current iccs pll sleep mode peripheral: 40 mhz *5 10 15 ma *1 high - speed cr sleep mode peripheral: 4 mhz * 2 1.2 4.4 ma *1 sub sleep mode peripheral: 32 khz *6 0.1 3.1 ma *1 low - speed cr sleep mode peripheral: 100 khz 0.1 3.1 ma *1 *1 : when a l l ports are fixed. *2 : when setting it to 4 mhz by trimming. * 3 : t a =+25c, v cc = 5.5 v * 4 : t a =+ 105 c, v cc =5.5 v *5 : when using the crystal oscillator of 4 mhz (including the current consumption of the oscillation circuit ) * 6 : when using the crystal oscillator of 32 khz (including the current consumption of the oscillation circuit )
document number: 002 - 04674 rev. *c page 63 of 116 mb9a310a series (vcc = avcc = 2.7v to 5.5v, usbvcc = 3.0v to 3.6v, vss = avss = 0v, t a = - 40 c to + 105 c ) parameter symbol pin name conditions value unit remarks typ * 2 max * 2 timer mode current i cct vcc main timer mode t a = + 25c, when lvd is off *3 2.5 3 ma *1 t a = + 105c, when lvd is off *3 - 6 ma *1 sub timer mode t a = + 25 c, when lvd is off *4 60 230 a *1 t a = + 105 c, when lvd is off *4 - 3.1 ma *1 stop mode current i cch stop mode t a = + 25 c, when lvd is off 35 200 a *1 t a = + 105 c, when lvd is off - 3 ma *1 *1: when a l l ports are fixed. * 2 : v cc =5.5 v *3: when using the crystal oscillator of 4 mhz (including the current consumption of the oscillation circuit ) * 4 : when using the crystal oscillator of 32 khz (including the current consumption of the oscillation circuit ) low - voltage detection current (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40c to + 105 c) parameter symbol pin name conditions value unit remarks typ max low - voltage detection circuit (lvd) power supply current i cclvd vcc at operation for interrupt vcc = 5.5 v 4 7 a at not detect flash memory current (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40c to + 105 c) parameter symbol pin name conditions value unit remarks typ max flash m emory w rite/ e rase current i ccflash vcc at write/erase 11.4 13.1 ma a/d converter current (v cc = av cc = 2.7v to 5.5v, v ss = av ss = avrl = 0v, t a = - 40c to + 105 c) parameter symbol pin name conditions value unit remarks typ max power supply current i ccad avcc at 1unit operation 0.57 0.72 ma at stop 0.06 20 a reference power supply current i ccavrh avrh at 1unit operation avrh=5.5 v 1.1 1.96 ma at stop 0.06 4 a
document number: 002 - 04674 rev. *c page 64 of 116 mb9a310a series 12.3.2 pin characteristics (vcc = avcc = 2 .7v to 5.5v, vss = avss = 0v, t a = - 40 c to + 105 c ) parameter symbol pin name conditions value unit remarks min typ max "h" level input voltage (hysteresis input) v ihs cmos hysteresis input pin, md0,1 - vcc 0.8 - vcc + 0.3 v 5v tolerant i/o pin - vcc 0.8 - vss + 5.5 v "l" level input voltage (hysteresis input) v ils cmos hysteresis input pin, md0,1 - vss - 0.3 - vcc 0.2 v "h" level output voltage v oh 4ma type vcc 4.5 v i oh = - 4 ma vcc - 0.5 - vcc v vcc < 4.5 v i oh = - 2 ma 12ma type vcc 4.5 v i oh = - 12 ma vcc - 0.5 - vcc v vcc < 4.5 v i oh = - 8 ma p80, p81 vcc 4.5 v i oh = - 20.5 ma vcc - 0.4 - vcc v vcc < 4.5 v i oh = - 13.0 ma "l" level output voltage v ol 4ma type vcc 4.5 v i ol = 4 ma vss - 0.4 v vcc < 4.5 v i ol = 2 ma 12ma type vcc 4.5 v i ol = 12 ma vss - 0.4 v vcc < 4.5 v i ol = 8 ma p80, p81 vcc 4.5 v i ol = 18.5 ma vss - 0.4 v vcc < 4.5 v i ol = 10.5 ma input leak current i il - - - 5 - + 5 a pull - up resistor value r pu pull - up pin v cc 4.5 v 25 50 100 k vcc < 4.5 v 30 80 200 input capacitance c in other than vcc, vss, avcc, avss, avrh - - 5 15 pf
document number: 002 - 04674 rev. *c page 65 of 116 mb9a310a series 12.4 ac characteristics 12.4.1 main clock input characteristics ( vcc = 2.7v to 5.5v, vss = 0v, t a = - 40 c to + 105 c ) parameter symbol pin name conditions value unit remarks min max input frequency f ch x0 x1 vcc 4.5 v 4 48 mhz when crystal oscillator is connected vcc < 4.5 v 4 20 vcc 4.5 v 4 48 mhz when using external c lock vcc < 4.5 v 4 20 input clock cycle t cylh vcc 4.5 v 20.83 250 ns when using external c lock vcc < 4.5 v 50 250 input clock pulse width - p wh /t cylh p wl /t cylh 45 55 % when using external c lock input clock rising time and falling time t cf t cr - - 5 ns when using external c lock internal operating clock * 1 frequency f cm - - - 40 mhz master clock f cc - - - 40 mhz base clock (hclk/fclk) f cp0 - - - 40 mhz apb0 bus clock * 2 f cp1 - - - 40 mhz apb1 bus clock * 2 f cp2 - - - 40 mhz apb2 bus clock * 2 internal operating clock * 1 cycle time t cycc - - 25 - ns base clock (hclk/fclk) t cycp0 - - 25 - ns apb0 bus clock * 2 t cycp1 - - 25 - ns apb1 bus clock * 2 t cycp2 - - 25 - ns apb2 bus clock * 2 *1 : for more information about each internal operating clock , see " chapter 2 - 1: clock " in " fm3 family peripheral manual ". *2 : for about each apb bus which each peripheral is connected to , see " 8 . block diagram " in this data sheet. x0
document number: 002 - 04674 rev. *c page 66 of 116 mb9a310a series 12.4.2 sub clock input characteristics ( vcc = 2.7v to 5.5v, vss = 0v, t a = - 40 c to + 105 c ) parameter symbol pin name conditions value unit remarks min typ max input frequency f cl x0a x1a - - 32.768 - khz when crystal oscillator is connected - 32 - 100 khz when using external clock input clock cycle t cyll - 10 - 31.25 s when using external clock input clock pulse width - p wh /t cyll p wl /t cyll 45 - 55 % when using external clock 12.4.3 built - in cr oscillation characteristics built - in h igh - speed cr ( vcc = 2.7v to 5.5v, vss = 0v, t a = - 40 c to + 105 c ) parameter symbol conditions value unit remarks min typ max clock frequency f crh t a = + 25 c 3.96 4 4.04 mhz when trimming * 1 t a = 0 c to + 70 c 3.84 4 4.16 t a = - 40 c to + 105 c 3.8 4 4.2 t a = - 40 c to + 105 c 3 4 5 when not trimming f requency stability time t crwt - - - 90 s *2 *1 : in the case of using the values in cr trimming area of flash memory at shipment for frequency trimming. *2 : f requency stable time is time to stable of the frequency of the high - speed cr clock after the trim value is set. after setting the trim value, the period when the frequency stability time passes can use the high - speed cr clock as a source clock. built - in low - speed cr ( vcc = 2.7v to 5.5v, vss = 0v, t a = - 40 c to + 105 c ) parameter symbol conditions value unit remarks min typ max clock frequency f crl - 50 100 150 k hz x0 a
document number: 002 - 04674 rev. *c page 67 of 116 mb9a310a series 12.4.4 operating conditions of main pll and usb pll (in the case of using main clock for input clock of pll) (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40 c to + 105 c) parameter symbol value unit remarks min typ max pll oscillation stabilization wait time (lock up time) * 1 t lock 100 - - s pll input clock frequency f plli 4 - 16 mh z pll multiple rate - 13 - 75 multiple pll macro oscillation clock frequency f pllo 200 - 300 mh z main pll clock frequency * 2 f clkpll - - 40 mh z usb clock frequency * 3 f clkspll - - 48 mh z after the m frequency division *1 : time from when the pll starts operating until the oscillation stabilizes. *2 : for more information about main pll clock (clkpll), see "c hapter 2 - 1 : clock" in "fm3 family peripheral manual". *3 : for more information about usb clock, see "c hapter 2 - 2 : usb clock generation" in "fm3 family peripheral manual communication macro part". 12.4.5 operating conditions of main pll (in the case of using the built - in hig h speed cr for the input clock of the m ain pll) ( vcc = 2.7v to 5.5v, vss = 0v, t a = - 40 c to + 105 c ) parameter symbol value unit remarks min typ max pll oscillation stabilization wait time (lock up time) * 1 t lock 100 - - s pll input clock frequency f plli 3.8 4 4.2 mh z pll multiple rate - 50 - 71 multiple pll macro oscillation clock frequency f pllo 190 - 300 mh z main pll clock frequency * 2 f clkpll - - 40 mh z * 1 : time from when the pll starts operating until the oscillation stabilizes. *2 : for more information about main pll clock (clkpll), see "c hapter 2 - 1 : clock" in "fm3 family peripheral manual". when setting pll multiple rate, please take the accuracy of the built - in high - speed cr clock into account and prevent the master clock from exceeding the maximum frequency. k divider pll input clock main pll pll macro oscillation clock m divider main pll clock (clkpll) n divider main pll connection high - speed cr clock (clkhc) main clock (clkmo)
document number: 002 - 04674 rev. *c page 68 of 116 mb9a310a series 12.4.6 reset input characteristics (vcc = 2.7v to 5.5v, v ss = 0v, t a = - 40 c to + 105 c ) parameter symbol pin name conditions value unit remarks min max reset input time t initx initx - 500 - n s 12.4.7 power - on reset timing ( v ss = 0v, t a = - 40 c to + 10 5 c ) parameter symbol pin name conditions value unit remarks min typ max power supply shut down time t off vcc - 5 0 - - ms *1 power ramp rate dv/dt vcc:0.2 v to 2.70 v 0.9 - 1000 mv/us *2 time until releasing power - on reset t prt - 0.446 - 0.744 ms *1: v cc must be held below 0.2 v for minimum period of t off . improper initialization may occur if this condition is not met. *2: this dv/dt characteristic is applied at the power - on of cold start (t off >50 ms). note: ? if t off cannot be satisfied designs must assert external reset(initx) at power - up and at any brownout event per 1 2 . 4. 6 . glossary vdh: detection voltage of low voltage detection reset. s ee 0 . low - v oltage d etection c haracteristics main clock (clkmo) k divider pll input clock usb pll m divider usb clock n divider usb pll connection pll macro oscillation clock v d h t p r t i n t e r n a l r s t v c c c p u o p e r a t i o n s t a r t r s t a c t i v e r e l e a s e 0 . 2 v 0 . 2 v t o f f d v / d t 0 . 2 v 2 . 7 v
document number: 002 - 04674 rev. *c page 69 of 116 mb9a310a series 12.4.8 external b us timing external bus clock output c haracteristics (vcc = 2.7v to 5.5v, v ss = 0v, t a = - 40 c to + 105 c ) parameter symbol pin name conditions value unit min max out put frequency t cycle mclkout vcc 4.5 v - 40 mhz vcc < 4.5 v - 32 mhz minimum c lock cycle time - vcc 4.5 v 25 - ns vcc < 4.5 v 31.25 - ns note: ? the external bus clock output is a divided clock of hclk. for more information about setting of clock divider, see " chapter 12: external bus interface" in "fm3 family peripheral manual" when external bus clock is not output, this characteristic does not give any effect on external bus operation. ex ternal bus signal input/output c haracteristics (vcc = 2.7v to 5.5v, vss = 0v, t a = - 40 c to + 105 c ) parameter symbol conditions value unit remarks signal input characteristics v ih - 0.8 v cc v v il 0.2 v cc v signal output characteristics v oh 0.8 v cc v v ol 0.2 v cc v mclkout input signal output signal v ih v il v il v ih v oh v ol v ol v oh
document number: 002 - 04674 rev. *c page 70 of 116 mb9a310a series separate bus access asynchronous sram mode ( vcc = 2.7v to 5.5v, vss = 0v, t a = - 40 c to + 105 c ) parameter symbol pin name conditions value unit min max moex min pulse width t oew moex vcc 4.5 v mclkn - 3 - ns vcc < 4.5 v mcsx address output delay time t csl C av mcsx[7:0] mad[24:0] vcc 4.5 v - 9 + 9 ns vcc < 4.5 v - 12 + 12 moex address hold time t oeh - ax moex mad[24:0] vcc 4.5 v 0 mclkm+9 ns vcc < 4.5 v mclkm+12 mcsx moex delay time t csl - oel moex mcsx[7:0] vcc 4.5 v mclkm - 9 mclkm+9 ns vcc < 4.5 v mclkm - 12 mclkm+12 moex mcsx time t oeh - csh vcc 4.5 v 0 mclkm+9 ns vcc < 4.5 v mclkm+12 mcsx mdqm delay time t csl - rdqml mcsx mdqm[1:0] vcc 4.5 v mclkm - 9 mclkm+9 ns vcc < 4.5 v mclkm - 12 mclkm+12 data set up moex time t ds - oe moex madata[15:0] vcc 4.5 v 20 - ns vcc < 4.5 v 38 - moex data hold time t dh - oe moex madata[15:0] vcc 4.5 v 0 - ns vcc < 4.5 v mwex min pulse width t wew mwex vcc 4.5 v mclkn - 3 - ns vcc < 4.5 v mwex address output delay time t weh - ax mwex mad[24:0] vcc 4.5 v 0 mclkm+9 ns vcc < 4.5 v mclkm+12 mcsx mwex delay time t csl - wel mwex mcsx[7:0] vcc 4.5 v mclkn - 9 mclkn+9 ns vcc < 4.5 v mclkn - 12 mclkn+12 mwex mcsx delay time t weh - csh vcc 4.5 v 0 mclkm+9 ns vcc < 4.5 v mclkm+12 mcsx mdqm delay time t csl - wdqml mcsx mdqm[1:0] vcc 4.5 v mclkn - 9 mclkn+9 ns vcc < 4.5 v mclkn - 12 mclkn+12 mcsx data output time t csl - dv mcsx madata[15:0] vcc 4.5 v mclk - 9 mclk+9 ns vcc < 4.5 v mclk - 12 mclk+12 mwex data hold time t weh - dx mwex madata[15:0] vcc 4.5 v 0 mclkm+9 ns vcc < 4.5 v mclkm+12 note: ? when the external load capacitance c l = 30 pf (m = 0 to 15, n = 1 to 16).
document number: 002 - 04674 rev. *c page 71 of 116 mb9a310a series mclk mcsx[7:0] mad[24:0] mdqm[1:0] mwex madata[15:0] moex i n v a l i d a d d r e s s t c s l - o e l t c s l - a v r d a d d r e s s w d t d h - o e t d s - o e t w e h - d x t o e w t o e h - a x t o e h - c s h t w e w t c y c l e t c s l - w e l t c s l - a v t w e h - c s h t w e h - a x t c s l - w d q m l t c s l - r d q m l t c s l - d v
document number: 002 - 04674 rev. *c page 72 of 116 mb9a310a series separate bus access synchronous sram mode ( vcc = 2.7v to 5.5v, vss = 0v, t a = - 40 c to + 105 c ) parameter symbol pin name conditions value unit min max address delay time t av mclk mad[24:0] vcc 4.5 v 1 9 ns vcc < 4.5 v 12 mcsx delay time t csl mclk mcsx[7:0] vcc 4.5 v 1 9 ns vcc < 4.5 v 12 t csh vcc 4.5 v 1 9 ns vcc < 4.5 v 12 moex delay time t rel mclk moex vcc 4.5 v 1 9 ns vcc < 4.5 v 12 t reh vcc 4.5 v 1 9 ns vcc < 4.5 v 12 data set up mclk time t ds mclk madata[15:0] vcc 4.5 v 19 - ns vcc < 4.5 v 37 mclk data hold time t dh mclk madata[15:0] vcc 4.5 v 0 - ns vcc < 4.5 v mwex delay time t wel mclk mwex vcc 4.5 v 1 9 ns vcc < 4.5 v 12 t weh vcc 4.5 v 1 9 ns vcc < 4.5 v 12 mdqm[1:0] delay time t dqml mclk mdqm[1:0] vcc 4.5 v 1 9 ns vcc < 4.5 v 12 t dqmh vcc 4.5 v 1 9 ns vcc < 4.5 v 12 mclk data output time t ods mclk, madata[15:0] v cc 4.5 v mclk+1 mclk+18 ns v cc < 4.5 v mclk+24 mclk data output time t od mclk madata[15:0] vcc 4.5 v 1 18 ns vcc < 4.5 v 1 24 note: ? when the external load capacitance c l = 30 pf. mclk mcsx[7:0] mad[24:0] mdqm[1:0] mwex madata[15:0] moex i n v a l i d t d q m l t r e h a d d r e s s t c s l t a v t r e l r d a d d r e s s w d t d q m h t w e h t w e l t d h t d s t o d t a v t c s h t c y c l e t d q m l t d q m h t o d s
document number: 002 - 04674 rev. *c page 73 of 116 mb9a310a series multiplexed bus access asynchronous sram mode ( vcc = 2.7v to 5.5v, vss = 0v, t a = - 40 c to + 105 c ) parameter symbol pin name conditions value unit min max multiplexed address delay time t a le - chmadv male madata[15:0] vcc 4.5 v 0 10 ns vcc < 4.5 v 20 multiplexed address hold time t c hmadh vcc 4.5 v mclk n+0 mclk n+10 ns vcc < 4.5 v mclk n+0 mclk n+20 note: ? when the external load capacitance c l = 30 pf (m = 0 to 15, n = 1 to 16). mclk mcsx[7:0] male moex mwex madata[15:0] mad [24:0] mdqm [1:0]
document number: 002 - 04674 rev. *c page 74 of 116 mb9a310a series multiplexed bus access synchronous sram mode (vcc = 2.7v to 5.5v, vss = 0v, t a = - 40 c to + 105 c ) parameter symbol pin name conditions value unit remarks min max male delay time t chal mclk ale vcc 4.5 v 1 9 ns vcc < 4.5 v 1 2 ns t chah vcc 4.5 v 1 9 ns vcc < 4.5 v 12 ns mclk multiplexed address delay time t chmadv m clk madata[15:0] vcc 4.5 v 1 t od ns vcc < 4.5 v mclk multiplexed data output time t chmad x vcc 4.5 v 1 t od ns vcc < 4.5 v note: ? when the external load capacitance c l = 30 pf. mclk mcsx[7:0] male moex mwex madata[15:0] mad [24:0] mdqm [1:0]
document number: 002 - 04674 rev. *c page 75 of 116 mb9a310a series external ready input timing (vcc = 2.7v to 5.5v, v ss = 0v, t a = - 40 c to + 105 c ) parameter symbol pin name conditions value unit remarks min max mclk mrdy input setup time t rdyi mclk mrdy vcc 4.5 v 19 - n s vcc < 4.5 v 37 when rdy is input when rdy is release d mclk original moex mwex mrdy mclk extended moex mwex mrdy over 2cycles t rdyi 2 cycles t rdyi 0.5vcc
document number: 002 - 04674 rev. *c page 76 of 116 mb9a310a series 12.4.9 base timer input timing timer input timing (vcc = 2.7v to 5.5v, v ss = 0v, t a = - 40 c to + 105 c ) parameter symbol pin name conditions value unit remarks min max input pulse width t tiwh t tiwl tioan/tiobn (when using as eck,tin) - 2 t cycp - ns trigger input timing (vcc = 2.7v to 5.5v, v ss = 0v, t a = - 40 c to + 105 c ) parameter symbol pin name conditions value unit remarks min max input pulse width t trgh , t trgl tioan/tiobn (when using as tgin) - 2 t cycp - n s note: ? t cycp indicates the apb bus clock cycle time. about the apb bus number which the base timer is c onnected to, see 8 . block diagram in this data sheet. eck tin tgin t tiwh v ihs v ihs v ils v ils t tiw l t trgh v ihs v ihs v ils v ils t trg l
document number: 002 - 04674 rev. *c page 77 of 116 mb9a310a series 12.4.10 csio/uart timing csio (spi = 0, scinv = 0) (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40 c to + 105 c) parameter symbol pin name conditions vcc < 4.5v vcc 4.5v unit min max min max baud rate - - - - 8 - 8 mbps serial clock cycle time t scyc sckx master mode 4t cycp - 4 t cycp - ns sck sot delay time t slovi sckx sotx - 30 + 30 - 20 + 20 ns sin sck setup time t ivshi sckx sinx 50 - 30 - ns sck sin hold time t shixi sckx sinx 0 - 0 - ns serial clock "l" pulse width t slsh sckx slave mode 2 t cycp - 10 - 2 t cycp - 10 - ns serial clock "h" pulse width t shsl sckx t cycp + 10 - t cycp + 10 - ns sck sot delay time t slove sckx sotx - 50 - 30 ns sin sck setup time t ivshe sckx sinx 10 - 10 - ns sck sin hold time t shixe sckx sinx 20 - 20 - ns sck falling time tf sckx - 5 - 5 ns sck rising time tr sckx - 5 - 5 ns notes: ? the above characteristics apply to clk synchronous mode. ? t cycp indicates the apb bus clock cycle time. about the apb bus number which mult i - function s erial is connected to, see 8 . block diagram in this data sheet. ? these characteristics only guarantee the same relocate port number. for example, the combination of sckx_0 and sotx_1 is not guaranteed. ? when the external load capacitance c l = 30 pf.
document number: 002 - 04674 rev. *c page 78 of 116 mb9a310a series master mode slave mode sck sot sin sck sot sin t scyc v oh v oh v ol v ol v ol v ih v il v ih v il t slovi t ivshi t shixi t slsh t shsl v ih t f tr v ih v oh v ih v il v il v ol v ih v il v ih v il t slove t ivshe t shixe
document number: 002 - 04674 rev. *c page 79 of 116 mb9a310a series csio (spi = 0, scinv = 1) ( vcc = 2.7v to 5.5v, vss = 0v, t a = - 40 c to + 105 c ) parameter symbol pin name conditions vcc < 4.5 v vcc 4.5 v unit min max min max baud rate - - - - 8 - 8 mbps serial clock cycle time t scyc sckx master mode 4 t cycp - 4 t cycp - ns sck sot delay time t shovi sckx sotx - 30 + 30 - 20 + 20 ns sin sck setup time t ivsli sckx sinx 50 - 30 - ns sck sin hold time t slixi sckx sinx 0 - 0 - ns serial clock "l" pulse width t slsh sckx slave mode 2 t cycp - 10 - 2 t cycp - 10 - ns serial clock "h" pulse width t shsl sckx t cycp + 10 - t cycp + 10 - ns sck sot delay time t shove sckx sotx - 50 - 30 ns sin sck setup time t ivsle sckx sinx 10 - 10 - ns sck sin hold time t slixe sckx sinx 20 - 20 - ns sck falling time tf sckx - 5 - 5 ns sck rising time tr sckx - 5 - 5 ns notes: ? the above characteristics apply to clk synchronous mode. ? t cycp indicates the apb bus clock cycle time. about the apb bus numbe r which multi - function s erial is connected to, see block diagram in this data sheet. ? these characteristics only guarantee the same relocate port number. for example, the combination of sckx_0 and sotx_1 is not guaranteed. ? when the external load capacitance c l = 30 pf.
document number: 002 - 04674 rev. *c page 80 of 116 mb9a310a series master mode slave mode sck sot sin sck sot sin t scyc v oh v oh v oh v ol v ol v ih v il v ih v il t shovi t ivsli t slixi t shsl t slsh v ih tf tr v ih v oh v il v il v il v ol v ih v il v ih v il t shove t ivsle t slixe
document number: 002 - 04674 rev. *c page 81 of 116 mb9a310a series csio (spi = 1, scinv = 0) ( vcc = 2.7v to 5.5v, vss = 0v, t a = - 40 c to + 105 c ) parameter symbol pin name conditions vcc < 4.5 v vcc 4.5 v unit min max min max baud rate - - - - 8 - 8 mbps serial clock cycle time t scyc sckx master mode 4 t cycp - 4 t cycp - ns sck sot delay time t shovi sckx sotx - 30 + 30 - 20 + 20 ns sin sck setup time t ivsli sckx sinx 50 - 30 - ns sck sin hold time t slixi sckx sinx 0 - 0 - ns sot sck delay time t sovli sckx sotx 2 t cycp - 30 - 2 t cycp - 30 - ns serial clock "l" pulse width t slsh sckx slave mode 2 t cycp - 10 - 2 t cycp - 10 - ns serial clock "h" pulse width t shsl sckx t cycp + 10 - t cycp + 10 - ns sck sot delay time t shove sckx sotx - 50 - 30 ns sin sck setup time t ivsle sckx sinx 10 - 10 - ns sck sin hold time t slixe sckx sinx 20 - 20 - ns sck falling time tf sckx - 5 - 5 ns sck rising time tr sckx - 5 - 5 ns notes: ? the above characteristics apply to clk synchronous mode. ? t cycp indicates the apb bus clock cycle time. about the apb b us number which multi - function s erial is connected to, see 8 . block diagram in this data sheet. ? these characteristics only guarantee the same relocate port number. for example, the combination of sckx_0 and sotx_1 is not guaranteed. ? when the external load capacitance c l = 30 pf.
document number: 002 - 04674 rev. *c page 82 of 116 mb9a310a series master mode slave mode *: changes when writing to tdr register sck sot sin sck sot sin t sovli t scyc t shovi v ol v ol v oh v oh v ol v oh v ol v ih v il v ih v il t ivsli t slixi tf tr t slsh t shsl t shove v il v il v ih v ih v ih v oh * v ol v oh v ol v ih v il v ih v il t ivsle t slixe
document number: 002 - 04674 rev. *c page 83 of 116 mb9a310a series csio (spi = 1, scinv = 1) ( vcc = 2.7v to 5.5v, vss = 0v, t a = - 40 c to + 105 c ) parameter symbol pin name conditions vcc < 4.5 v vcc 4.5 v unit min max min max baud rate - - - - 8 - 8 mbps serial clock cycle time t scyc sckx master mode 4 t cycp - 4 t cycp - ns sck sot delay time t slovi sckx sotx - 30 + 30 - 20 + 20 ns sin sck setup time t ivshi sckx sinx 50 - 30 - ns sck sin hold time t shixi sckx sinx 0 - 0 - ns sot sck delay time t sovhi sckx sotx 2 t cycp - 30 - 2 t cycp - 30 - ns serial clock "l" pulse width t slsh sckx slave mode 2 t cycp - 10 - 2 t cycp - 10 - ns serial clock "h" pulse width t shsl sckx t cycp + 10 - t cycp + 10 - ns sck sot delay time t slove sckx sotx - 50 - 30 ns sin sck setup time t ivshe sckx sinx 10 - 10 - ns sck sin hold time t shixe sckx sinx 20 - 20 - ns sck falling time tf sckx - 5 - 5 ns sck rising time tr sckx - 5 - 5 ns notes: ? the above characteristics apply to clk synchronous mode. ? t cycp indicates the apb bus clock cycle time. about the apb b us number which multi - function s erial is connected to, see 8 . block diagram in this data sheet. ? these characteristics only guarantee the same reloc ate port number. for example, the combination of sckx_0 and sotx_1 is not guaranteed. ? when the external load capacitance c l = 30 pf.
document number: 002 - 04674 rev. *c page 84 of 116 mb9a310a series master mode slave mode uart e xternal clock input (ext = 1) ( vcc = 2.7v to 5.5v, vss = 0v, t a = - 40 c to + 105 c ) parameter symbol conditions min max unit remarks serial clock " l" pulse width t slsh c l = 30 pf t cycp + 10 - ns serial clock " h" pulse width t shsl t cycp + 10 - ns sck falling time tf - 5 ns sck rising time tr - 5 ns sck sot sin sck sot sin s ck t scyc t slovi v ol v oh v oh v oh v ol v oh v ol v ih v il v ih v il t ivshi t shixi t sovhi t shsl tr t slsh tf t slove v il v il v il v ih v ih v ih v oh v ol v oh v ol v ih v il v ih v il t ivshe t shixe t shsl v i l v i l v i l v ih v ih v ih tr tf t slsh
document number: 002 - 04674 rev. *c page 85 of 116 mb9a310a series 12.4.11 external input timing ( vcc = 2.7v to 5.5v, vss = 0v, t a = - 40 c to + 105 c ) parameter symbol pin name conditions value unit remarks min max input pulse width t inh t inl adtg - 2 t cycp * - ns a/d converter trigger input frckx free - run timer input clock icxx input capture dttixx - 2 t cycp * - ns wave form generator intxx, nmix except timer mode, stop mode 2 t cycp + 100 * - ns external interrupt nmi timer mode, stop mode 500 - ns *1: t cycp indicates the apb bus clock cycle time. about the apb bus number which the a/d converter, multi - function timer, external i nterrupt are connected to, see 8 . block diagram in this data sheet.
document number: 002 - 04674 rev. *c page 86 of 116 mb9a310a series 12.4.12 quadrature position/revolution counter timing (vcc = 2.7v to 5.5v, vss = 0v, t a = - 40 c to + 105 c ) parameter symbol conditions value unit min max ain pin "h" width t ahl - 2 t cycp * - ns ain pin "l" width t all - bin pin "h" width t bhl - bin pin "l" width t bll - bin rise time from ain pin "h" level t aubu pc_mode2 or pc_ m ode3 ain fall time from bin pin "h" level t buad pc_mode2 or pc_mode3 bin fall time from ain pin "l" level t adbd pc_mode2 or pc_mode3 ain rise time from bin pin "l" level t bdau pc_mode2 or pc_mode3 ain rise time from bin pin "h" level t buau pc_mode2 or pc_mode3 bin fall time from ain pin "h" level t aubd pc_mode2 or pc_mode3 ain fall time from bin pin "l" level t bdad pc_mode2 or pc_mode3 bin rise time from ain pin "l" level t adbu pc_mode2 or pc_mode3 zin pin "h" width t zhl qcr:cgsc = "0" zin pin "l" width t zll qcr:cgsc = "0" ain/bin rise and fall time from determined zin level t zabe qcr:cgsc = "1" determined zin level from ain/bin rise and fall time t abez qcr:cgsc = "1" *: t cycp indicates the apb bus clock cycle time. about the apb bus number which quadrature position/revolution counter is connected to, see " 8 . block diagram " in this data sheet. ain bin t aubu t buad t adbd t bdau t ahl t all t bhl t bll
document number: 002 - 04674 rev. *c page 87 of 116 mb9a310a series zin zin ain/bin bin t buau t aubd t bdad t adbu t bhl t bll t ahl t all ain
document number: 002 - 04674 rev. *c page 88 of 116 mb9a310a series 12.4.13 i 2 c timing (vcc = 2.7v to 5.5v, vss = 0v, t a = - 40 c to + 105 c ) parameter symbol conditions standard - mode fast - mode unit remarks min max min max scl clock frequency f scl c l = 30 pf, r = (vp/i ol )* 1 0 100 0 400 khz (repeated) start condition hold time sda scl t hdsta 4.0 - 0.6 - s sclclock "l" width t low 4.7 - 1.3 - s sclclock "h" width t high 4.0 - 0.6 - s (repeated) start condition setup time scl sda t susta 4.7 - 0.6 - s data hold time scl sda t hddat 0 3.45* 2 0 0.9* 3 s data setup time sda scl t sudat 250 - 100 - ns stop condition setup time scl sda t susto 4.0 - 0.6 - s bus free time between "stop condition" and "start condition" t buf 4.7 - 1.3 - s noise filter t sp - 2t cycp * 4 - 2t cycp * 4 - ns * 1 ; r and c represent the pull - up resistance and load capacitance of the scl and sda lines, respectively. vp indicates the power supply voltage of the pull - up resistance and i ol indicates v ol guaranteed current. *2 : the maximum t hddat must satisfy that it doesn't extend at least "l" period (t low ) of device's scl signal. *3 : fast - mode i 2 c bus device can be used on s tandard - mode i 2 c bus system as long as the device satisfies the requirement of "t sudat 250 ns". *4 : t cycp is the apb bus clock cycle time. about the apb bus number that i 2 c is connected to, see " 8 . block diagram " in this data sheet. to use standard - mode, set the apb bus clock at 2 mhz or more. to us e fast - mode, set the apb bus clock at 8 mhz or more. sda s cl
document number: 002 - 04674 rev. *c page 89 of 116 mb9a310a series 12.4.14 etm timing ( vcc = 2.7v to 5.5v, vss = 0v, t a = - 40 c to + 105 c ) parameter symbol pin name conditions value unit remarks min max data hold t etmh traceclk traced[3:0] vcc 4.5 v 2 9 ns vcc < 4.5 v 2 15 traceclk frequency 1/t trace traceclk vcc 4.5 v - 40 mhz vcc < 4.5 v - 32 mhz traceclk c lock cycle time t trace vcc 4.5 v 25 - ns vcc < 4.5 v 31.25 - ns note: ? when the external load capacitance c l = 30 pf. hclk traceclk traced[3:0]
document number: 002 - 04674 rev. *c page 90 of 116 mb9a310a series 12.4.15 jtag timing ( vcc = 2.7v to 5.5v, vss = 0v, t a = - 40 c to + 105 c ) parameter symbol pin name conditions value unit remarks min max tms, tdi setup time t jtags tck tms,tdi vcc 4.5 v 15 - n s vcc < 4.5 v tms, tdi hold time t jtagh tck tms,tdi vcc 4.5 v 15 - n s vcc < 4.5 v tdo delay time t jtagd tck tdo vcc 4.5 v - 25 n s vcc < 4.5 v - 45 note: ? when the external load capacitance c l = 30 pf. tck tms/ tdi tdo
document number: 002 - 04674 rev. *c page 91 of 116 mb9a310a series 12.5 12 - bit a/d converter electrical characteristics for the a/d converter (vcc = avcc = 2 .7v to 5.5v, vss = avss = 0v, t a = - 40 c to + 105 c ) parameter symbol pin name value unit remarks min typ max resolution - - - - 12 bit integral nonlinearity - - - 1.7 4.5 lsb avrh = 2.7 v to 5.5 v differential nonlinearity - - - 1.7 2.5 lsb zero transition voltage v zt anxx - 8 15 mv full - scale transition voltage v fst anxx - avrh8 avrh15 mv conversion time - - 1.0* 1 - - s avcc 4.5 v 1.2* 1 avcc < 4.5 v sampling time ts - *2 - - ns avcc 4.5 v *2 - - avcc < 4.5 v compare clock cycle* 3 tcck - 50 - 2000 ns state transition time to operation permission tstt - - - 1.0 s analog input capacity c ain - - - 12.9 pf analog input resistor r ain - - - 2 k avcc 4.5 v 3.8 avcc < 4.5 v interchannel disparity - - - - 4 lsb analog port input leak current - anxx - - 5 a analog input voltage - anxx avss - avrh v reference voltage - avrh 2.7 - avcc v *1: the conversion time is the value of sampling time (ts) + compare time (tc). the condition of the minimum conversion time is the following. avcc 4.5 v, hclk= 40 mhz sampling time: 300 ns, compare time: 700 ns avcc < 4.5 v, hclk= 40 mhz sampling time: 500 ns, compare time: 700 ns ensure that it satisfies the value of the sampling time (ts) and compare clock cycle (tcck). for setting of the sampling time and compare clock cycle, see " chapter 1 - 1 : a/d converter" in "fm3 family peripheral manual analog mac ro part". the a/d converter register is set at apb bus clock timing. the sampling clock and compare clock are set at base clock (hclk). about the apb bus number which the a/d converter is connected to, see " 8 . block diagram " in this data sheet. *2: a necessary sampling time changes by external impedance. ensure that it set the sam pling time to satisfy (equation 1) *3: the compare time (tc) is the value of (equation 2)
document number: 002 - 04674 rev. *c page 92 of 116 mb9a310a series (equation 1) ts ( r ain + r ext ) c ain 9 ts : sampling time r ain : i nput resistor of a/d = 2 k 4.5 v av cc 5.5 v i nput resist or of a/d = 3.8 k 2.7 v av cc < 4.5 v c ain : i nput capacity of a/d = 12.9 pf 2.7 v av cc 5.5 v r ext : output impedance of external circuit (equation 2) tc = tcck 14 tc : compare time tcck : compare clock cycle r ext r ain c ain analog signal source an xx analog input pin c omparator
document number: 002 - 04674 rev. *c page 93 of 116 mb9a310a series definition of 12 - bit a/d converter terms ? resolution: analog variation that is recognized by an a/d converter. ? integral nonlinearity: deviation of the line betwee n the zero - transition point (0b000000000000 0b000000000001) and the full - scale transition point (0b111111111110 0b111111111111) from the actual conversion characteristics. ? differential nonlinearity: deviation from the ideal value of the i nput voltage that is required to change the output code by 1 lsb. integral nonlinearity of digital output n = v nt - {1lsb (n - 1) + v z t } [lsb] 1lsb differential nonlinearity of digital output n = v (n + 1) t - v nt - 1 [lsb] 1lsb 1lsb = v fst C z t 4094 n: a/d converter digital output value. v z t : voltage at which the digital output changes from 0x000 to 0x001. v fst : voltage at which the digital output changes from 0xffe to 0xfff. v nt : voltage at which the digital output changes from 0x(n ? 1) to 0xn. i ntegral nonl inearity differential non linearity digital output digital output actual conversion characteristics actual conversion characteristics ideal characteristics (actually - measured value) actual conversion characteristics actual conversion characteristics (actually - measured value) (actually - measured value) ideal characteristics (actually - measured value) analog input analog input (actually - measured value) 0x001 0x002 0x003 0x004 0x f fd 0x f fe 0x f ff av ss avrh av ss avrh 0x(n - 2) 0x(n - 1) 0x(n+1) 0xn {1 lsb(n - 1) + v zt } v nt v fst v zt v nt v (n+1)t
document number: 002 - 04674 rev. *c page 94 of 116 mb9a310a series 12.6 usb characteristics ( vcc = 2.7v to 5.5v, usbvcc = 3.0v to 3.6v, vss = 0v, t a = - 40 c to + 105 c ) parameter symbol pin name conditions value unit remarks m in m ax input charact - eristics input high level voltage v ih udp0, udm0 - 2.0 usbvcc + 0.3 v *1 input low level voltage v il - vss - 0.3 0.8 v *1 differential input sensitivity v di - 0.2 - v *2 different common mode range v cm - 0.8 2.5 v *2 output charact - eristics output high level voltage v oh external pull - down resistance = 15 k 2.8 3.6 v *3 output low level voltage v ol external pull - up resistance = 1.5 k 0.0 0.3 v *3 crossover voltage v crs - 1.3 2.0 v *4 rising time t fr full speed 4 20 ns *5 falling time t ff full speed 4 20 ns *5 rise/fall time matching t frfm full speed 90 111.11 % *5 output impedance z drv full speed 28 44 *6 rising time t lr low speed 75 300 ns *7 falling time t lf low speed 75 300 ns *7 rise/fall time matching t lrfm low speed 80 125 % *7 *1: the switching threshold voltage of single - end - receiver of usb i/o buf fer is set as within v il (max) = 0.8 v, v ih (min) = 2.0 v (ttl input standard). there are some hysteres es to lower noise sensitivity. *2: use differential - receiver to receive usb differential data signal. differential - receiver has 200 mv of differential input sensitivity when the differential data input is within 0.8 v to 2.5 v to the local ground reference level. above voltage range is the common mode input voltage range. common mode input voltage [v] minimum differential input sensitivity [v]
document number: 002 - 04674 rev. *c page 95 of 116 mb9a310a series *3 : the output drive capability of the driver is below 0.3 v at low - state (v ol ) (to 3.6 v and 1.5 k load), and 2.8 v or above (to the ground and 1.5 k load) at high - state (v oh ). *4 : the cross voltage of the external differential output signal (d + /d ?) of usb i/o buffer is within 1.3 v to 2.0 v. *5: they indicate ris ing time (trise) and fall ing time (tfall) of the full - speed differential data signal. they are defined by the time between 10% and 90% of the output signal voltage. for full - speed buffer, tr/tf ratio is regulated as within 10% to minimize rfi emission. v crs specified range rising time falling time
document number: 002 - 04674 rev. *c page 96 of 116 mb9a310a series *6 : usb full - speed connection is performed via twist pair cable shield with 90 15% characteristic impedance(differential mode). usb standard defines that output impedance of usb driver must be in range from 28to 44. so, discrete series resist or (rs) addition is defined in order to satisfy the above definition and keep balance. when using this usb i/o, use it with 25 to 30 (recommendation value 27) series resistor rs. rs series resistor 25 to 30 series resistor of 27 (recommendation value) must be added. and, use "resistance with an uncertainty of 5% by e24 sequence". *7 : they indicate ris ing time (trise) and fall ing time (tfall) of the low - speed differential data signal. they are defined by the time between 10% and 90% of the output signal voltage. see " low - speed load (compliance load)" for conditions of external load. mount it as external resistance. 28 44 equiv. imped. 28 44 equiv. imped.
document number: 002 - 04674 rev. *c page 97 of 116 mb9a310a series low - speed load (upstream port load) - reference 1 low - speed load (downstream port load) - reference 2 low - speed load (compliance load) c l = 50pf to 150pf c l = 50pf to 150pf c l =200pf to 600pf c l =200pf to 600pf c l = 200pf to 450pf c l = 200pf to 450pf
document number: 002 - 04674 rev. *c page 98 of 116 mb9a310a series 12.7 low - v oltage d etection c haracteristics low - v oltage d etection r eset ( t a = - 40 c to + 105 c) parameter symbol conditions value unit remarks min typ max detected voltage vdl - 2.25 2.45 2.65 v when voltage drops released voltage vdh - 2.30 2.50 2.70 v when voltage rises interrupt of low - voltage detection ( t a = - 40 c to + 105 c ) parameter symbol conditions value unit remarks min typ max detected voltage vdl svhi = 0000 2.58 2.8 3.02 v when voltage drops released voltage vdh 2.67 2.9 3.13 v when voltage rises detected voltage vdl svhi = 0001 2.76 3.0 3.24 v when voltage drops released voltage vdh 2.85 3.1 3.34 v when voltage rises detected voltage vdl svhi = 0010 2.94 3.2 3.45 v when voltage drops released voltage vdh 3.04 3.3 3.56 v when voltage rises detected voltage vdl svhi = 0011 3.31 3.6 3.88 v when voltage drops released voltage vdh 3.40 3.7 3.99 v when voltage rises detected voltage vdl svhi = 0100 3.40 3.7 3.99 v when voltage drops released voltage vdh 3.50 3.8 4.10 v when voltage rises detected voltage vdl svhi = 0111 3.68 4.0 4.32 v when voltage drops released voltage vdh 3.77 4.1 4.42 v when voltage rises detected voltage vdl svhi = 1000 3.77 4.1 4.42 v when voltage drops released voltage vdh 3.86 4.2 4.53 v when voltage rises detected voltage vdl svhi = 1001 3.86 4.2 4.53 v when voltage drops released voltage vdh 3.96 4.3 4.64 v when voltage rises lvd stabilization wait time t lvdw - - - 2240 t cycp * s * : t cycp indicates the apb2 bus clock cycle time.
document number: 002 - 04674 rev. *c page 99 of 116 mb9a310a series 12.8 flash memory write/erase characteristics 12.8.1 write / erase time ( vcc = 2.7v to 5.5v , t a = - 40 c to + 105 c ) parameter value unit remarks typ * max * sector erase time large sector 0. 7 3.7 s includes write time prior to internal erase small sector 0.3 1.1 half word (16 - bit) write time 12 384 s not including system - level overhead time chip erase time 64k/128k/256kbyte 5.2 23.6 s includes write time prior to internal erase 384k/512kbyte 8 38.4 s *: the typical value is immediately after shipment , the maximum value is guarantee value under 100,000 cycle of erase/write . 12.8.2 erase/write cycles and data hold time erase/write cycles (cycle) data hold time (year ) remarks 1,000 20* 10,000 10* 100,000 5* *: at average + 85 c
document number: 002 - 04674 rev. *c page 100 of 116 mb9a310a series 12.9 return time from low - power consumption mode 12.9.1 return factor: interrupt the return time from low - power consumption mode is indicated as follows. it is from receiving the return factor to starting the program operation. return count tim e ( v cc = 2.7v to 5.5v , t a = - 40 c to + 105 c ) parameter symbol value unit remarks typ max* sleep mode ticnt t cycc ns high - speed cr timer mode, main timer mode, pll timer mode 40 80 s low - speed cr timer mode 453 737 s sub timer mode 453 737 s stop mode 453 737 s *: the maximum value depends on the accuracy of built - in cr. operation example of return from low - power consumption mode (by external interrupt*) * : external interrupt is set to detecting fall edge. e x t . i n t t i c n t i n t e r r u p t f a c t o r a c c e p t c p u o p e r a t i o n s t a r t a c t i v e i n t e r r u p t f a c t o r c l e a r b y c p u
document number: 002 - 04674 rev. *c page 101 of 116 mb9a310a series operation example of return from low - power consumption mode (by internal resource interrupt*) *: internal resource interrupt is not included in return factor by the kind of low - power consumption mode. notes: ? the return factor is different in each l ow - p ower consumption modes. see " chapter 6 : low power consumption mode" and "operations of standby modes" in fm3 family peripheral manual about the return factor from l ow - p ower consumption mode. ? when interrupt reco veries, the operation mode that cpu recoveries depends on the state before the low - power consumption mode transition. see " chapter 6 : low power consumption mode" in "fm3 family peripheral manual ". i n t e r n a l r e s o u r c e i n t t i c n t i n t e r r u p t f a c t o r a c c e p t c p u o p e r a t i o n s t a r t a c t i v e i n t e r r u p t f a c t o r c l e a r b y c p u
document number: 002 - 04674 rev. *c page 102 of 116 mb9a310a series 12.9.2 return factor: reset the return time from low - power consumption mode is indicated as follows. it is from releasing reset to starting the program operation. return count time ( v cc = 2.7v to 5.5v , t a = - 40 c to + 105 c ) parameter symbol value unit remarks typ max* sleep mode trcnt 308 444 s high - speed cr timer mode, main timer mode, pll timer mode 308 444 s low - speed cr timer mode 428 684 s sub timer mode 428 684 s stop mode 428 684 s *: the maximum value depends on the accuracy of built - in cr. operation example of return from low - power consumption mode (by initx) i n i t x t r c n t i n t e r n a l r s t c p u o p e r a t i o n s t a r t r s t a c t i v e r e l e a s e
document number: 002 - 04674 rev. *c page 103 of 116 mb9a310a series operation example of return from low power consumption mode (by internal resource reset*) *: internal resource reset is not included in return factor by the kind of low - power consumption mode. notes: ? the return factor is different in each low - power consumption modes. see chapter 6 : low power consumption mode and operations of standby modes in fm3 family peripheral manual . ? when interrupt reco veries, the operation mode that cpu recoveries depends on the state before the low - power consumption mode transition. see chapter 6 : low power consumption mode in fm3 family peripheral manual . ? the time during the power - on reset/low - voltage detection re set is excluded. see 12.4.7 . power - on reset timing in 12.4 . ac characteristics in 12 electrical characteristics . electrical characteristics for the detail on the time during the power - on reset/low - voltage detection reset. ? when in recovery from reset, cpu changes to the high - speed cr run mode. when using the main clock or the pll clock, it is necessary to add the main clock oscillation stabilization wait time or the main pll clock stabilization wait time. ? the internal resource reset means the watchdog reset and the csv reset. i n t e r n a l r e s o u r c e r s t t r c n t i n t e r n a l r s t c p u o p e r a t i o n s t a r t r s t a c t i v e r e l e a s e
document number: 002 - 04674 rev. *c page 104 of 116 mb9a310a series 13. orderi ng information part number on - chip flash memory on - chip sram package packing mb9af311lapmc1 - g - jne2 64 kbyte 16 kbyte plastic , lqfp (0.5 mm pitch),64 - pin ( lqd064 ) tray mb9af312lapmc1 - g - jne2 128 kbyte 16 kbyte mb9af314lapmc1 - g - jne2 256 kbyte 32 kbyte mb9af311lapmc - g - jne2 64 kbyte 16 kbyte plastic , lqfp (0.65 mm pitch),64 - pin ( lqg064 ) mb9af312lapmc - g - jne2 128 kbyte 16 kbyte mb9af314lapmc - g - jne2 256 kbyte 32 kbyte mb9af311laqn - g - ave2 64 kbyte 16 kbyte plastic , qfn (0.5 mm pitch),64 - pin ( vnc064 ) mb9af312laqn - g - ave2 128 kbyte 16 kbyte mb9af314laqn - g - ave2 256 kbyte 32 kbyte mb9af311mapmc - g - jne2 64 kbyte 16 kbyte plastic , lqfp (0.5 mm pitch),80 - pin ( lqh080 ) mb9af312mapmc - g - jne2 128 kbyte 16 kbyte mb9af314mapmc - g - jne2 256 kbyte 32 kbyte mb9af315mapmc - g - jne2 384 kbyte 32 kbyte mb9af316mapmc - g - jne2 512 kbyte 32 kbyte mb9af311napmc - g - jne2 64 kbyte 16 kbyte plastic , lqfp (0.5 mm pitch),100 - pin ( lqi100 ) mb9af312napmc - g - jne2 128 kbyte 16 kbyte mb9af314napmc - g - jne2 256 kbyte 32 kbyte mb9af315napmc - g - jne2 384 kbyte 32 kbyte mb9af316napmc - g - jne2 512 kbyte 32 kbyte mb9af311napf - g - jne1 64 kbyte 16 kbyte plastic , qfp (0.65 mm pitch), 100 - pin ( pqh100 ) mb9af312napf - g - jne1 128 kbyte 16 kbyte mb9af314napf - g - jne1 256 kbyte 32 kbyte mb9af315napf - g - jne1 384 kbyte 32 kbyte mb9af316napf - g - jne1 512 kbyte 32 kbyte mb9af311nabgl - ge1 64 kbyte 16 kbyte plastic , pfbga (0.8 mm pitch),112 - pin ( lbc112 ) mb9af312nabgl - ge1 128 kbyte 16 kbyte mb9af314nabgl - ge1 256 kbyte 32 kbyte
document number: 002 - 04674 rev. *c page 105 of 116 mb9a310a series 14. package dimensions package type package code lqfp 100 lqi100 002 - 1 15 00 * a n o t e s : 1 . a ll d i m e n s io n s a r e i n m i ll i m e t e r s . 2. d a t u m pla n e h i s lo c a t e d a t t h e bot t o m of t h e mold partin g li n e coi n c i d e n t w i t h w h e r e t h e l e a d e x i t s t h e body . 3 . d a tums a - b a n d d t o b e d e t e rmi n e d a t d a t u m p l a n e h . 4. to b e d e t e r m i n e d a t s e a t i n g plane c . 5 . d i m e n sio n s d1 a nd e 1 d o n ot i nc l ud e m ol d p r o t ru si o n . allowable protrusi o n is 0 . 25 mm p r e si d e . d i m e n s i o n s d 1 a n d e 1 i n c l u d e m o l d m i s m a t c h a n d a r e d e t e rmine d a t d a t u m plane h . 6 . d e t a i l s o f p i n 1 i d e n t i f i e r a r e o p t i o n a l b u t m u s t be l o c ate d w i t h i n th e zo n e i n d i c a t e d . 7 . r e g a r d l e s s of t h e r e l a t i v e s i z e o f t h e u p p e r a n d l o w e r b o d y s e c t i o n s . d i m e n s i o n s d 1 a n d e 1 a r e d e t e r m i n e d a t t h e larges t f e a t u r e o f t h e b o d y e x c l u s i v e o f m o l d f l a s h a n d g a te burrs . b u t i n clu d i n g a n y m i s m a t c h b e t w e e n t h e u p p e r a nd lowe r s e c t ion s of t h e mol d e r b o dy . 8 . d i m e n s i o n b d o e s n o t i n c l u d e d a m b a r p r o t r u s i o n . t h e d a mba r p r o t r u s i o n ( s ) s h a l l n o t c a u s e t h e l e a d w i d t h to e x c e e d b m a x i m u m b y m o r e t h a n 0 . 0 8 m m . d a m b a r c a n n o t b e l o cated o n t h e l o w e r r a d i u s o r t h e l e a d f oot . 9. t h e s e d i m e n s ion s a p p l y t o t h e fla t s e c t i o n of the lea d b e t w e e n 0 . 10m m a n d 0.25 m m f r o m t h e lead tip . 10 . a 1 i s d e f i n e d a s t h e d i s t a n c e f r om t h e s e a t i n g p l a n e t o t h e low e s t p o i n t of t h e p a c k age body . d im e n s io n s symbol m in . n o m . max . a 1.7 0 a1 0.0 5 0.1 5 b 0 .1 5 0 .2 7 c 0 .0 9 0 .2 0 d 1 6 . 00 bsc d 1 1 4 .00 bs c e 0 . 50 bsc e e1 l 0 .4 5 0 .6 0 0 .7 5 l1 0.3 0 0.5 0 0.7 0 1 6. 00 bsc 1 4. 00 bsc a a 1 0.25 0.0 8 c 1 100 d 1 d e 1 e e 4 4 0.0 8 c a - b d 7 5 seat i n g pla n e 0.2 0 c a - b d 0.1 0 c a - b d b se c t io n a-a ' c 9 a a ' 5 7 5 7 3 3 6 8 1 0 2 2 l1 l b d 1 d e 1 e 4 4 5 7 5 7 25 26 50 51 75 76 side v i ew top v i ew b o tt o m vie w d e t a il a 1 25 26 50 5 7 1 5 100 76 package ou t line, 1 00 le a d l q f p 14.0x14.0x1.7 mm lq i 100 r ev * a
document number: 002 - 04674 rev. *c page 106 of 116 mb9a310a series package type package code qfp 100 pqh100 002 - 1 5 156 ** d i mensi o n s s ymb o l m i n . n o m . max. a 3 . 3 5 a 1 0. 0 5 0. 4 5 b 0 . 2 7 0 . 3 2 0 . 3 7 c 0 . 1 1 0 . 2 3 d 2 3 . 9 0 b sc d 1 2 0 . 0 0 b sc e 0 .6 5 bsc e e1 l 0 . 7 3 0 . 8 8 1 . 0 3 l 1 1 . 9 5 r ef l 2 0.2 5 bs c 1 7 . 9 0 b sc 1 4 . 0 0 b sc 0 8 l 2 0 3 1 10 0 e b d1 d 5 7 4 e e 1 3 6 4 5 7 0 . 2 0 c a - b d 7 5 2 0 . 1 3 c a - b d 8 0 . 4 0 c a - b d 3 2 s e a t i n g p l an e b s e cti o n a - a ' c 9 s i d e vie w t o p vie w a a ' 0 . 1 0 c 1 0 d e t a il a 3 1 5 0 5 1 8 0 8 1 1 3 0 10 0 3 1 5 0 0 8 1 5 8 1 b o tt o m vie w package ou t line, 100 lea d q fp 20 . 00x14.00x3 . 35 mm p q h 100 r ev * *
document number: 002 - 04674 rev. *c page 107 of 116 mb9a310a series package type package code lqfp 80 lqh080 002 - 11501 ** d i men s io n s m i n . n o m . m ax . 0 7 . 1 a a 1 0 . 0 5 0 . 1 5 b 0 .1 5 0 .2 7 c 0 .0 9 0 .2 0 d 1 4 . 0 0 b s c . d 1 12.00 b s c . e 0 . 5 0 bs c e e 1 l 0 . 4 5 0 . 6 0 0 . 7 5 l 1 0 . 3 0 0 . 5 0 0 . 7 0 1 4 . 0 0 b s c . 1 2 . 0 0 b s c . s y m b o l b o t t o m vie w a a 1 0 . 2 5 1 8 0 d 1 d e b d 0. 2 0 c a - b d 0. 1 0 c a - b d 0. 0 8 c a - b d e e 1 4 5 7 3 4 5 7 3 8 7 5 2 1 0 b s e c t i o n a - a ' c 9 2 s ea t i n g p l an e 0. 0 8 c a a ' 6 l 1 l s i de vie w t o p vie w 2 0 2 1 4 0 1 4 0 6 6 1 0 6 1 4 8 0 6 1 2 1 4 0 1 2 0 package ou t line, 80 le a d lq f p 12.0x12.0x1.7 mm lq h 080 r e v * *
document number: 002 - 04674 rev. *c page 108 of 116 mb9a310a series package type package code lqfp 64 lqd064 002 - 11499 ** d i m e nsion s s y m b o l min . n o m . max . 0 7 . 1 a a1 0.0 0 0.2 0 b 0.1 5 0. 2 c 0.0 9 0.2 0 d 12 . 00 bsc. d 1 10 . 00 bsc. e 0 .50 bsc e e1 l 0.4 5 0.6 0 0.7 5 l 1 0.3 0 0.5 0 0.7 0 12 . 00 bsc. 10 . 00 bsc. d 1 d e 1 1 6 6 4 4 5 7 e e 1 4 5 7 3 6 3 0.2 0 c a - b d b 0.1 0 c a - b d 0.0 8 c a - b d 8 7 5 2 a a 1 0 . 25 10 b se c t ion a-a ' c 9 l1 l 2 a a ' s e a t i n g plan e 0.0 8 c side v i e w top v i e w b o tt o m vie w 1 7 3 2 3 3 4 8 4 9 1 1 6 1 7 3 2 3 3 4 8 6 4 4 9 package ou t line, 64 le a d lq f p 10 . 0x10 . 0x1 . 7 mm l q d064 re v * *
document number: 002 - 04674 rev. *c page 109 of 116 mb9a310a series package type package code lqfp 64 lqg064 002 - 13881 ** dimensi o n sym b o l m i n . no m . m ax . a 1.7 0 a 1 0.0 0 0.2 0 b 0 . 2 7 0 . 3 2 0 . 3 7 c 0 . 0 9 0 . 20 d 14.00 bsc d 1 12.00 bsc e 0.65 bsc e e 1 l 0.4 5 0.6 0 0.7 5 l1 0.3 0 0.5 0 0.7 0 14.00 bsc 12.00 bsc 0 d 1 d e 1 16 64 e e 1 4 5 7 4 5 7 3 3 0.20 c a - b d b 0.10 c a - b d 0.13 c a - b d 8 7 5 2 2 0.10 c a a' s eati n g pla n e b s ec t i on a - a' c 9 a a 1 0.2 5 1 0 l1 l s i d e vie w t o p v i e w b o tt o m vie w 17 32 33 48 49 1 16 17 32 64 49 8 4 3 3 12 . 0x12 . 0x1 . 7 m m lq g 064 r ev * * package ou t line, 6 4 lea d lq f p
document number: 002 - 04674 rev. *c page 110 of 116 mb9a310a series package type package code pfbga 112 lbc112 002 - 13225 ** n i s t h e n u m b e r o f p o p u l a t e d s o l d e r b a l l p o s i t i o n s f o r m a trix w hen t here i s an even number of s o l d e r ba ll s i n t h e o u t e r r o w , w hen t here i s an o dd number of s o l d e r ba ll s i n t h e o u t e r r o w , d e f i n e t h e positio n of t h e c e n t e r s o ld e r b a ll in t h e o u t e r r o w . " s d " and " se " are measured w i th r espe c t to d a t u m s a a nd b a nd s y m b o l " m e " i s t h e b a l l m a t r i x s i z e i n t h e " e " d i r e c t io n . s y m b o l " m d " i s t h e b a l l m a t r i x s i z e i n t h e " d " d i r e c t io n . "e" represents the sol d e r ba ll g r i d p i t ch . di m e n s i on " b " i s m e a s u r e d a t t h e m a x i m u m b a l l di a m e t e r in a so l d er bal l posi t i o n des i gna t i o n per jep 9 5 , sect i o n 3 , spp-020 . " + " i nd i cates the the o ret i cal c e n t e r of d ep o p u l a t e d s o l d e r a 1 c o r n e r t o b e i d e n t i f i e d b y c h amf e r, la s e r or i n k m a r k 8 . 7 . 6 . no t es : 5 . 4 . 3 . 2 . 1 . a l l di m e n s i on s a r e i n m i l l i m e t e r s . s d b e e e d m e n 0 . 3 5 0 . 0 0 0 . 8 0 bs c 0 . 8 0 bs c 0 . 4 5 11 2 1 1 0 . 5 5 d i m e n s io n s d1 m d e 1 e d a a 1 s y m b o l 0 . 2 5 m i n . - 8 . 0 0 bs c 8 . 0 0 bs c 1 1 1 0 . 0 0 bs c 1 0 . 0 0 bs c n o m . - 1 . 4 5 0 . 4 5 m ax . s e 0 . 0 0 0 . 3 5 m e t a l i z e d m a r k , i n d e n t a t i o n o r o t h e r m e a n s. " s d " = e d / 2 a n d " s e " = e e / 2 . plane parallel t o d a t u m c . " s d " or " s e " = 0 . siz e md x m e . b a ll s . a 0 . 20 c 2 x b 0 . 20 c 2 x i n d e x ma rk pin a 1 c o rne r 7 1 2 3 4 5 6 7 8 9 1 0 1 1 a b c d e f g h j k l 11 2 x b 0 . 08 c a b 5 6 6 s i d e vie w 0 . 10 c c d e t a il a b o tt o m vie w t o p vie w d e t a i l a 10 . 00x10 . 00 x1.45 mm l b c 112 r ev * * package ou t line, 11 2 ball f b g a
document number: 002 - 04674 rev. *c page 111 of 116 mb9a310a series package type package code qfn 64 vnc064 002 - 13234 ** dimen s io n s n o m. m i n . b e 6.00 bs c 9.00 bs c d a 1 a 9.00 bs c 0.00 sym b o l ma x . 0.90 0.05 0.50 bs c l 0.35 0.45 0.40 0.2 0 0.2 5 0.30 e d 2 2 6.00 bs c e n 64 0.20 ref r n d 1 6 b i late r al c o p l a n a r it y zo n e a p pli e s to the exposed heat p i n # 1 i d o n t o p w i l l b e l o c a t e d w i t h i n t h e i n d i c a t e d z o n e. m a x i m u m a l l o w a b l e b u r r i s 0 . 0 7 6 m m i n a l l d i r e c t i o n s. d i m e n s i o n " b " a p p l i e s t o m e t a l l i z e d t e r m i n a l a n d i s m eas ur ed n i s t h e t o t a l n u m b e r o f t e r m i n a l s . a l l d i m e n sio n s a r e i n m i l l i m e t e r s . d i m e n s i o n i n g a n d t o l e r a n c i n g c o n f o r m s t o a s m e y 1 4 . 5 m-1994 . n o tes: ma x . p a c k age w a r p age i s 0.05mm . 8 7 . 6 . 5 1 . 4 3 . 2 . 9 h a s t h e optio n a l r a d i u s o n t h e ot h e r e n d of t h e te rm i n a l , t h e d i me n sio n " b " s h o uld n ot b e me a s u r e d i n t h at r a d i u s a r ea. n d r e f e r s to t h e n u m b e r of t e rmi n als o n d s i d e or e side . s i n k slug a s w e ll a s t h e t e rminals . be tw een 0 . 15 and 0 . 30mm f r o m t erm i n a l ti p . if t h e t e rm i n a l s i de vie w b o tt om vie w t o p vie w d a e b 0. 1 0 c 2 x 0. 1 0 c 2 x 0. 1 0 c a a 1 0. 0 5 c c seating plan e d2 e 2 0. 1 0 c a b 0. 1 0 c a b 1 6 4 e b 0. 1 0 c a b 0. 0 5 c ( n d - 1 ) e index m ar k 8 4 5 l 9 1 6 1 7 3 2 8 4 3 3 4 9 6 4 4 9 1 6 3 3 1 4 8 1 7 3 2 p a c k a ge o ut l i n e , 64 l ea d q f n 9 . 0 x 9 . 0 x0 . 9 m m v nc 0 64 6 . 0 x6 . 0 m m e pa d ( s aw n ) r e v*. *
document number: 002 - 04674 rev. *c page 112 of 116 mb9a310a series 15. errata this chapter describes the errata for mb9a310 product family . details include errata trigger conditions, scope of impact, available workaround, and silicon revision applicability. contact your local cypress sales representative if you have questions. 15.1 part num bers affected 15.2 qualification status product status: in production ? qual. 15.3 errata summary this table defines the errata applicability to available devices. items p art number silicon revision fix status watch counter issue refer to 15.1 rev. initial rev. fixed in rev. a watch counter issue ? problem definition the underflow interruption does not occur. ? parameters affected n/a ? trigger condition(s) the condition is when underflow interruption occurs. ? scope of impact the underflow interruption does not occur as specified. ? workaround this error cannot be avoided by any software, except not u sing watch counter interrupt. ? fix status this issue was fixed in rev. a. part number initial revision mb9af311l pmc1 - g - jne2 , mb9af31 2 l pmc1 - g - jne2 , mb9af31 4 l pmc1 - g - jne2 , mb9af311lpmc - g - jne2 , mb9af31 2 l pmc - g - jne2 , mb9af31 4 lpmc - g - jne2 , mb9af311l qn - g - av e2 , mb9af31 2 l qn - g - av e2 , mb9af31 4 l qn - g - av e2 , mb9af311 m pmc - g - jne2 , mb9af31 2m pmc - g - jne2 , mb9af31 4m pmc - g - jne2 , mb9af31 5m pmc - g - jne2 , mb9af31 6m pmc - g - jne2 , mb9af311 n pmc - g - jne2 , mb9af31 2n pmc - g - jne2 , mb9af31 4n pmc - g - jne2 , mb9af31 5n pmc - g - jne2 , mb9af31 6n pmc - g - jne2 , mb9af311 npf - g - jne 1, mb9af31 2npf - g - jne 1, mb9af31 4npf - g - jne 1, mb9af31 5n p f - g - jne 1, mb9af31 6n p f - g - jne 1, mb9af311n bgl - ge1 , mb9af31 2 n bgl - ge1 , mb9af31 4 n bgl - ge1
document number: 002 - 04674 rev. *c page 113 of 116 mb9a310a series 16. major changes spansion publication number: ds706 - 0001 2 page section change results revision 1.0 - - initial release revision 2.0 - - revised series name and part number: mb9a310 series mb9a310a series mb9af311l mb9af311la mb9af312l mb9af312la mb9af314l mb9af314la mb9af311m mb9af311ma mb9af312m mb9af312ma mb9af314m mb9af314ma mb9af315m mb9af315ma mb9af316m mb9af316ma mb9af311n mb9af311na mb9af3 12n mb9af312na mb9af314n mb9af314na mb9af315n mb9af315na mb9af316n mb9af316na added the following package. lcc - 64p - m24 7 product lineup ? function multi - function serial added the following description. ch.4 to ch.7: fifo (16steps 9 - bit) ch.0 to ch.3: no fifo external interrupts corrected the following description. 7pins (max) 8pins (max) 34 to 37 signal description multi - function serial (ch.0 to ch.7) corrected the description for function. added " lin pin " deleted " uart pin " 42, 43 i/o circuit type corrected the following schematic for " typeb " . cmos level hysteresis input digital input corrected the following schematic for " typec " . control pin digital output 51 handling device power supply pins corrected the description. 54 memory size ? added " memory size " . 69 electrical characteristics 4. ac characteristics (1)main clock input characteristics ? added the items f cm to the internal operating clock frequency. 71 (4 - 2) operating conditions of main pll ? added the description. 72 (7) external bus timing external bus clock out put characteristics ? 79 (8) base timer input timing trigger input timing ? added the note . 88 (10) external input timing ? corrected the footnote. 94 5. 12 - bit a/d converter (1) electrical characteristics for the a/d converter ? corrected the value of " full - scale transition voltage ". min: - 20 avrh - 20 max: +20 avrh+20 corrected the value of "compare clock cycle". max: 10000 2000 corrected the value of "reference voltage ". min: avss 2.7 revision 2.1 - - company name and layout design change revision 3.0 2 features usb interface added the description of pll for usb
document number: 002 - 04674 rev. *c page 114 of 116 mb9a310a series page section change results 3 features external bus interface added the description of maximum area size 9 packages deleted fpt - 64p - m24, fpt - 64p - m23, fpt - 80p - m21, fpt - 100p - m20 44, 46 i/o circuit type added the description of i 2 c to the type of e, f and i 44, 45 i/o circuit type added about +b input 51 handling devices added " s tabilizing power supply voltage" 51 handling devices c rystal oscillator circuit added the following description "evaluate oscillation of your using crystal oscillator by your mount board." 52 handling devices c pin changed the description 53 block diagram modified the block diagram 54 memory size changed to the following description see "memory size" in "product lineup" to confirm the memory size. 55 memory map memory map(1) modified the area of " external device area" 56, 57 memory map memory map(2)(3) added the summary of flash memory sector and the note 64, 65 electrical characteristics 1. absolute maximum ratings added the clamp maximum current added the output current of p80 and p81 added about +b input 66 electrical characteristics 2. recommended operation conditions modified the minimum value of analog reference voltage added smoothing capacitor added the note about less than the minimum power supply voltage 67, 68 electrical characteristics 3. dc characteristics (1) current rating changed the table format added main timer mode current added flash memor y current moved a/d converter current 71 electrical characteristics 4. ac characteristics (3) built - in cr oscillation characteristics added frequency stability time at built - in high - speed cr 72 electrical characteristics 4. ac characteristics (4 - 1) operating conditions of main and usb pll (4 - 2) operating conditions of main pll added main pll clock frequency added usb clock frequency added the figure of main pll connection and usb pll connection 73 electrical characteristics 4. ac characteristics (6) power - on reset timing added time until releasing power - on reset changed the figure of timing 75 - 77 electrical characteristics 4. ac characteristics (7) external bus timing modified data output time 82 - 89 electrical characteristics 4. ac characteristics (8) csio/uart timing modified from uart timing to csio/uart timing changed from internal shift clock operation to master mode changed from external shift clock operation to slave mode 96 electrical characteristics 5. 12bit a/d converter added the typical value of integral nonlinearity, differential nonlinearity, zero transition voltage and full - scale transition voltage modified stage transition time to operation permission modified the minimum value of reference voltage 105 - 108 electrical characteristics 9. return time from low - power consumption mode added return time from low - power consumption mode 109 ordering information change to full part number 110 package dimensions deleted fpt - 64p - m24, fpt - 64p - m23, fpt - 80p - m21, fpt - 100p - m20 note : please see document history about later revised information.
document number: 002 - 04674 rev. *c page 115 of 116 mb9a310a series document history document title: mb9a310a series 32 - bit arm? cortex? - m3 fm3 microcontroller document number: 002 - 04674 revision ecn orig. of change submission date description of change ** C akih 12/16/2014 migrated to cypress and assigned document number 002 - 0 4674 . no change to document contents or format. *a 51988 94 akih 0 4 / 06 /201 6 updated to cypress format. *b 5490454 yska 03 / 0 9 /201 7 changed package codes as follows ftp - 64p - m38 - > lqd064 , ftp - 64p - m39 - > lqg064 lcc - 64p - m24 - > vnc064 , fpt - 80p - m37 - >lqh080 fpt - 100p - m23 - >lqi100 , ftp - 100p - m06 - > pqh100 b ga - 112p - m04 - > lbc112 2 packages( p age 8 ) , 3 pin assignment( p age 9 to 14 ) , 12.2 recommended operating conditions( p age 61 ) , 13 ordering information( p age 104 ), 14 package dimensions( p age 105 - 111 ) changed j - tag to jtag in 4 list of pin functions ( p age 28 ). added note in 4 list of pin functions ( p age 39 ). updated 12.4.7 power - on reset timing ( pa ge 68 ) added 15. errata( page 112 ) change the name from usb function to usb device ( page 1, 7 , 3 8 ) corrected the following statement analog port input current ? analog port input leak current in chapter 12.5. 12 - bit a/d converter ( page 9 1 ) added the baud rate spec in 12.4.10 csio/ uart timing ( page 77 , 79 , 81 , 83 ) *c 5768636 ysat 06/12/2017 adapted new cypress logo
document number: 002 - 04674 rev. *c june 12, 2017 page 116 of 116 mb9a310a series sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution centers, manufacturers representatives, and distributors. to find the office closest to you , visit us at cypress locations . products arm ? cortex ? microcontrollers cypress.com/a rm automotive cypress.com/automotive clocks & buffers cypress.com/clocks interface cypress.com/interface internet of things cypress.com/iot memory cypress.com/memory m icrocontrollers cypress.com/m cu psoc cypres s.com/psoc power management ics cypress.com/p mic touch sensing cypress.com/touch usb controllers cypress.com/ usb wireless/rf cypress.com/wireless psoc? solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp | psoc 6 cypress developer community forums | wiced iot forums | projects | video | blogs | training | co mp onents technical s upport cypress.com/support arm and cortex are the registered trademarks of arm limited in the eu and other countries. all other trademarks or registered trademarks referenced herein are the property of their respective owners. ? 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